Patents by Inventor Yan DUAN

Yan DUAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210069903
    Abstract: Various embodiments of the present technology generally relate to robotic devices and artificial intelligence. More specifically, some embodiments relate to a robotic device for picking items from a bin and perturbing items in a bin. The robotic device may include one or more picking elements and one or more perturbation elements for disturbing a present arrangement of items in the bin. In an exemplary embodiment, a perturbation element comprises a compressed air valve. In some implementations, the robotic device may also include one or more computer-vision systems. Based on image data from the one or more computer-vision systems, a strategy for picking up items from the bin is determined. When no strategies with high probability of success exist, the robotic device may perturb the contents of the bin to create new available pick-up points.
    Type: Application
    Filed: September 8, 2020
    Publication date: March 11, 2021
    Inventors: Yan Duan, Ian Rust, Andrew Amir Vaziri, Xi Chen, Carlos Florensa
  • Patent number: 10461757
    Abstract: An apparatus, comprising a first sampling circuit configured to sample a clock signal according to a data signal to produce a first sampled signal, a second sampling circuit configured to sample the clock signal according to a delay signal to produce a second sampled signal, and a control circuit coupled to the first sampling circuit and the second sampling circuit, wherein the control circuit is configured to perform a not-and (NAND) operation according to the first sampled signal and the second sampled signal to produce an activation signal for activating a frequency adjustment for the clock signal.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: October 29, 2019
    Assignee: Futurewei Technologies, Inc.
    Inventors: Liang Gu, Yuming Cao, Gong Lei, Yen Dang, Yifan Gu, Hungyi Lee, Mamatha Deshpande, Shou-Po Shih, Yan Duan
  • Patent number: 10122348
    Abstract: A multiplexer comprises: an output circuit comprising a multiplexer output; and a first buffer coupled to the output circuit and comprising: a first selection input configured to receive a first selection signal; a first logical input configured to receive a first logical input signal; and a first ground; wherein the multiplexer is configured to: couple the first logical input to the multiplexer output when the first selection signal is a first value; and couple the first logical input to the first ground when the first selection signal is a second value. A method comprises: receiving a selection signal and a first logical input signal; coupling a first logical input to a multiplexer output when the selection signal is a first value; and coupling the first logical input to a ground when the selection signal is a second value.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: November 6, 2018
    Assignee: Futurewei Technologies, Inc.
    Inventors: Liang Gu, Yuming Cao, Gong Lei, Yen Dang, Yifan Gu, Hungyi Lee, Mamatha Deshpande, Shou-Po Shih, Yan Duan
  • Patent number: 10116470
    Abstract: An apparatus comprising an input port configured to receive an input signal propagated through a transmission link, wherein the transmission link comprises a low-frequency channel loss and a high-frequency channel loss, a continuous-time linear equalization (CTLE) circuit coupled to the input port and configured to produce an output signal according to the input signal by applying a first gain to the input signal at a first frequency to compensate the low-frequency loss, and applying a second gain to the input signal at a second frequency to compensate the high-frequency channel loss, and an output port coupled to the CTLE circuit and configured to output the output signal.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: October 30, 2018
    Assignee: Futurewei Technologies, Inc.
    Inventors: Liang Gu, Yuming Cao, Yen Dang, Gong Lei, Hungyi Lee, Yifan Gu, Mamatha Deshpande, Shou-Po Shih, Yan Duan
  • Patent number: 9941958
    Abstract: An apparatus comprising a semiconductor chip that comprises an optical modulator configured to modulate an optical signal based on a received driver signal, a voltage-mode (VM) driver coupled to the optical modulator and configured to produce a level-shifted driver signal to modulate the optical signal, and a two-stage test interface coupled to the optical modulator and configured to receive and test the level shifted driver signal. The two-stage test interface comprises a voltage equalization stage coupled to an output-terminated buffer stage, the VM driver comprises a two-stage VM Mach-Zehnder modulator (MZM) driver that comprises a pre-driver coupled to a VM level-shifter (VMLS). The apparatus further comprises a resistor coupled to an output of the buffer stage, wherein the resistor comprises an amount of resistance that matches a termination resistance of a test equipment. The termination resistance is about 50 ohm (?).
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: April 10, 2018
    Assignee: Futurewei Technologies, Inc.
    Inventors: Liang Gu, Yuming Cao, Yifan Gu, Hungyi Lee, Gong Lei, Yen Dang, Mamatha Deshpande, Shou-Po Shih, Yan Duan
  • Publication number: 20170288652
    Abstract: A multiplexer comprises: an output circuit comprising a multiplexer output; and a first buffer coupled to the output circuit and comprising: a first selection input configured to receive a first selection signal; a first logical input configured to receive a first logical input signal; and a first ground; wherein the multiplexer is configured to: couple the first logical input to the multiplexer output when the first selection signal is a first value; and couple the first logical input to the first ground when the first selection signal is a second value. A method comprises: receiving a selection signal and a first logical input signal; coupling a first logical input to a multiplexer output when the selection signal is a first value; and coupling the first logical input to a ground when the selection signal is a second value.
    Type: Application
    Filed: March 30, 2016
    Publication date: October 5, 2017
    Inventors: Liang Gu, Yuming Cao, Gong Lei, Yen Dang, Yifan Gu, Hungyi Lee, Mamatha Deshpande, Shou-Po Shih, Yan Duan
  • Publication number: 20170170894
    Abstract: An apparatus comprising a semiconductor chip that comprises an optical modulator configured to modulate an optical signal based on a received driver signal, a voltage-mode (VM) driver coupled to the optical modulator and configured to produce a level-shifted driver signal to modulate the optical signal, and a two-stage test interface coupled to the optical modulator and configured to receive and test the level shifted driver signal. The two-stage test interface comprises a voltage equalization stage coupled to an output-terminated buffer stage, the VM driver comprises a two-stage VM Mach-Zehnder modulator (MZM) driver that comprises a pre-driver coupled to a VM level-shifter (VMLS). The apparatus further comprises a resistor coupled to an output of the buffer stage, wherein the resistor comprises an amount of resistance that matches a termination resistance of a test equipment. The termination resistance is about 50 ohm (?).
    Type: Application
    Filed: December 15, 2015
    Publication date: June 15, 2017
    Inventors: Liang Gu, Yuming Cao, Yifan Gu, Hungyi Lee, Gong Lei, Yen Dang, Mamatha Deshpande, Shou-Po Shih, Yan Duan
  • Publication number: 20170126443
    Abstract: An apparatus comprising an input port configured to receive an input signal propagated through a transmission link, wherein the transmission link comprises a low-frequency channel loss and a high-frequency channel loss, a continuous-time linear equalization (CTLE) circuit coupled to the input port and configured to produce an output signal according to the input signal by applying a first gain to the input signal at a first frequency to compensate the low-frequency loss, and applying a second gain to the input signal at a second frequency to compensate the high-frequency channel loss, and an output port coupled to the CTLE circuit and configured to output the output signal.
    Type: Application
    Filed: October 28, 2015
    Publication date: May 4, 2017
    Inventors: Liang Gu, Yuming Cao, Yen Dang, Gong Lei, Hungyi Lee, Yifan Gu, Mamatha Deshpande, Shou-Po Shih, Yan Duan
  • Publication number: 20170126236
    Abstract: An apparatus, comprising a first sampling circuit configured to sample a clock signal according to a data signal to produce a first sampled signal, a second sampling circuit configured to sample the clock signal according to a delay signal to produce a second sampled signal, and a control circuit coupled to the first sampling circuit and the second sampling circuit, wherein the control circuit is configured to perform a not-and (NAND) operation according to the first sampled signal and the second sampled signal to produce an activation signal for activating a frequency adjustment for the clock signal.
    Type: Application
    Filed: December 29, 2016
    Publication date: May 4, 2017
    Inventors: Liang Gu, Yuming Cao, Gong Lei, Yen Dang, Yifan Gu, Hungyi Lee, Mamatha Deshpande, Shou-Po Shih, Yan Duan
  • Patent number: 9584303
    Abstract: An apparatus, comprising a first sampling circuit configured to sample a clock signal according to a data signal to produce a first sampled signal, a second sampling circuit configured to sample the clock signal according to a delay signal to produce a second sampled signal, and a control circuit coupled to the first sampling circuit and the second sampling circuit, wherein the control circuit is configured to perform a not-and (NAND) operation according to the first sampled signal and the second sampled signal to produce an activation signal for activating a frequency adjustment for the clock signal.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: February 28, 2017
    Assignee: Futurewei Technologies, Inc.
    Inventors: Liang Gu, Yuming Cao, Gong Lei, Yen Dang, Yifan Gu, Hungyi Lee, Mamatha Deshpande, Shou-Po Shih, Yan Duan
  • Patent number: 9339880
    Abstract: A face hobbing cutter system for face hobbing spiral bevel gears. The system includes at least one set of detachable cartridge assemblies having a plurality of respective cartridge assemblies. Each cartridge assembly includes a plurality of cartridges and indexable milling inserts. A part of the inserts of each set of cartridge assemblies are rhombic, tangential-mounted inserts for milling flanks of spiral bevel gear teeth, while the other inserts are grooving inserts, which are arranged transversely to the tangential-mounted inserts, for milling roots of spiral bevel gear teeth. The tangential-mounted inserts of each set of cartridge assemblies are provided in pairs, one being provided with its front facing the central axis, and the other being provided with its front facing away the central axis, to respectively mill concave curved flanks and convex curved flanks of the spiral bevel gear teeth.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: May 17, 2016
    Assignee: SANDVIK INTELLECTUAL PROPERTY AB
    Inventors: Tong Jia, Yan Duan
  • Publication number: 20140136440
    Abstract: There is provided a method that includes matching records from a plurality of international import/export databases, to unique corporate identifiers, and merging data from the records into a global database. There is also provided a system that employs the method, and a storage device that contains instructions that cause a processor to execute the method.
    Type: Application
    Filed: August 29, 2013
    Publication date: May 15, 2014
    Applicant: THE DUN & BRADSTREET CORPORATION
    Inventors: Adnan AHMED, Yan DUAN, Jerry RONAGHAN, Andres BENVENUTO, Anthony J. SCRIFFIGNANO, Michael KLEIN
  • Publication number: 20140101146
    Abstract: A method for generating a relevance score for at least one candidate retrieved in a search, the method comprising: initiating a query seeking at least one the candidate based upon at least one filter selected from the group consisting of: product name, product category, company name, HS code, SIC code and any other product-related qualifier; searching at least one database for matches between the candidate and the filter, thereby generating at least one matched candidate; generating an initial relevance score for each the matched candidate; generating at least one additional score for each the matched candidate, wherein the additional score is at least one selected from the group consisting of: a reputation score, a score boost, a past behavior score, a profile match score, a preference match score and a web behavior score; and generating a final relevance score based upon the initial relevance score and the at least one additional score for each the matched candidate.
    Type: Application
    Filed: August 30, 2013
    Publication date: April 10, 2014
    Applicant: THE DUN & BRADSTREET CORPORATION
    Inventors: Anthony J. SCRIFFIGNANO, Michael KLEIN, Sudip CHAKRABORTY, Mark STREITMAN, Adnan AHMED, Joseph CASTAGLIOLA, Yan DUAN, Andres BENVENUTO, Hiu Tai CHAN