Abstract: The applicant provides a compound for enhancing the space coupling degree of an endothelial cell ion channel complex TRPV4-KCa2.3 and anti-hypertension applications thereof. By finding the structural domains of the interacting sites of the endothelial cell ion channel complex TRPV4-KCa2.3, a compound with specificity which can act at the two interacting sites is prepared in the present invention. It is found that the compound can enhance the space coupling degree of the TRPV4-KCa2.3 complex and has great significance for the research and development of anti-hypertension drugs.

Abstract: The applicant provides a compound for enhancing the space coupling degree of an endothelial cell ion channel complex TRPV4-KCa2.3 and anti-hypertension applications thereof. By finding the structural domains of the interacting sites of the endothelial cell ion channel complex TRPV4-KCa2.3, a compound with specificity which can act at the two interacting sites is prepared in the present invention. It is found that the compound can enhance the space coupling degree of the TRPV4-KCa2.3 complex and has great significance for the research and development of anti-hypertension drugs.

Abstract: A flip-flop circuit may include a first latch and a second latch. The first latch, which may operate as a “master” latch, includes a first input terminal to receive a data signal, a second input terminal to receive a clock signal, and an output terminal. The second latch, which may operate as a “slave” latch, includes a first input terminal connected directly to the output terminal of the first latch, a second input terminal to receive the clock signal, and an output terminal to provide an output signal. The first latch and the second latch are to be clocked on the same phase of the clock signal, thereby eliminating the need to include clock inversion circuits that generate complementary clock signals.

Abstract: A CMOS D-type flip flop (D-FF) exhibits reduced power consumption by selectively disabling certain charging/discharging operations at specific circuit elements to minimize the capacitance of the circuit's internal nodes using a partial signaling technique. A clock inverter module may be used to provide a partial inverse clock signal that is the complement of a clock signal when a non-clock dependent input to the clock inverter module has a first value and to provide a fixed signal when the non-clock dependent signal has a second value. One or more MOSFETs controlled by the partial inverse clock signal do not charge or discharge when the non-clock dependent signal has the second value.

Abstract: A flip-flop circuit may include a first latch and a second latch. The first latch, which may operate as a “master” latch, includes a first input terminal to receive a data signal, a second input terminal to receive a clock signal, and an output terminal. The second latch, which may operate as a “slave” latch, includes a first input terminal connected directly to the output terminal of the first latch, a second input terminal to receive the clock signal, and an output terminal to provide an output signal. The first latch and the second latch are to be clocked on the same phase of the clock signal, thereby eliminating the need to include clock inversion circuits that generate complementary clock signals.

Abstract: A clock-gating circuit is disclosed that may reduce unnecessary power consumption associated with clock distribution networks. For some embodiments, the clock-gating circuit includes a latch control circuit, a storage latch, and a logic gate. The control circuit has inputs to receive an input clock signal, a clock enable signal, and a clock gating control signal, and has an output terminal to generate a latch enable signal. The latch has a data terminal responsive to the clock enable signal, a latch enable terminal responsive to the latch enable signal, and an output to generate the clock gating control signal. The logic gate has inputs to receive the input clock signal and the clock gating control signal, and has an output terminal to generate an output clock signal.

Abstract: A System and a method are disclosed for suppressing rush current noise in a power switch cell. The system comprises: a power switch (306) having an operational condition dependent upon the state of a control signal; and an inrush current limiter module (300) for outputting the control signal. The control signal transitions from a first value to an intermediate value and from the intermediate value to a second value, wherein the power switch is configured to operate in a low conductive (OFF) condition when the control signal has the first value, to operate in a high conductive (ON) condition when the control signal has the second value, and to operate in a moderately conductive condition when the control signal has the intermediate value. Therefore, when the power switch transitions from the OFF condition to the ON condition, the rush current noise may be reduced.

Abstract: Gate-rounding fabrication techniques can be implemented to increase an effective channel length of a transistor and to consequently reduce the leakage current and static power consumption associated with the transistor. The transistor comprises a substrate region that includes a source region and a drain region. The transistor can also comprise a gate region that includes a main gate portion, one or more gate tips, and one or more corresponding gate-rounded portions. Each of the one or more gate tips is formed at a suitable position along the side of the main gate portion. During fabrication, the junction between the main gate region and each of the gate tips takes on a rounded shape to form a corresponding gate-rounded region. The gate-rounded regions increase the average length of the gate region and the effective channel length of the transistor.

Abstract: A circuit and a method are disclosed for adjusting a body bias voltage applied to a power gating switch. The circuit comprises: a first supply voltage (916), a body bias generator (918) formed from a plurality of series connected MOSFETs coupled to a second supply voltage (928) and an adaptive switch (910) providing an output coupled to either the first supply voltage or the body bias generator output (926), wherein the output of the adaptive switch is a first body bias voltage when coupled to the first supply voltage and is a second body bias voltage when coupled to the body bias generator output such that the first body bias voltage is greater than the second body bias voltage when configured as a gating header switch and the first body bias voltage is less than the second body bias voltage when configured as a gating footer switch.

Abstract: A CMOS D-type flip flop (D-FF) exhibits reduced power consumption by selectively disabling certain charging/discharging operations at specific circuit elements to minimize the capacitance of the circuit's internal nodes using a partial signaling technique. A clock inverter module may be used to provide a partial inverse clock signal that is the complement of a clock signal when a non-clock dependent input to the clock inverter module has a first value and to provide a fixed signal when the non-clock dependent signal has a second value. One or more MOSFETs controlled by the partial inverse clock signal do not charge or discharge when the non-clock dependent signal has the second value.

Abstract: A clock-gating circuit is disclosed that may reduce unnecessary power consumption associated with clock distribution networks. For some embodiments, the clock-gating circuit includes a latch control circuit, a storage latch, and a logic gate. The control circuit has inputs to receive an input clock signal, a clock enable signal, and a clock gating control signal, and has an output terminal to generate a latch enable signal. The latch has a data terminal responsive to the clock enable signal, a latch enable terminal responsive to the latch enable signal, and an output to generate the clock gating control signal. The logic gate has inputs to receive the input clock signal and the clock gating control signal, and has an output terminal to generate an output clock signal.

Abstract: Gate-rounding fabrication techniques can be implemented to increase an effective channel length of a transistor and to consequently reduce the leakage current and static power consumption associated with the transistor. The transistor comprises a substrate region that includes a source region and a drain region. The transistor can also comprise a gate region that includes a main gate portion, one or more gate tips, and one or more corresponding gate-rounded portions. Each of the one or more gate tips is formed at a suitable position along the side of the main gate portion. During fabrication, the junction between the main gate region and each of the gate tips takes on a rounded shape to form a corresponding gate-rounded region. The gate-rounded regions increase the average length of the gate region and the effective channel length of the transistor.