Abstract: A method performed by a server computer is disclosed. The method comprises generating a binary compositional code matrix from an input matrix. The binary compositional code matrix is then converted into an integer code matrix. Each row of the integer code matrix is input into a decoder, including plurality of codebooks, to output a summed vector for each row. The method then includes inputting a derivative of each summed vector into a downstream machine learning model to output a prediction.

Abstract: An insulated gate bipolar transistor, comprising an anode second conductivity-type region and an anode first conductivity-type region provided on a drift region; the anode first conductivity-type region comprises a first region and a second region, and the anode second conductivity-type region comprises a third region and a fourth region, the dopant concentration of the first region being less than that of the second region, the dopant concentration of the third region being less than that of the fourth region, the third region being provided between the fourth region and a body region, the first region being provided below the fourth region, and the second region being provided below the third region and located between the first region and the body region.

Abstract: A processing method of a brittle material is provided, which includes: cutting a contour line of a preset standard hole and a plurality of breaking guide line groups located within the contour line on a workpiece by a first laser, one end of a breaking guide line of the breaking guide line groups being connected with the contour line and the other end of the breaking guide line extending within the contour line; heating and pre-breaking the contour line and the breaking guide line on the workpiece by a second laser; processing a blanking hole within the contour line on the workpiece by a non-thermal processing, the extended end of the breaking guide line extending into the blanking hole; and breaking along the contour line and the breaking guide line on the workpiece to form a standard hole in the workpiece.

Abstract: The present invention discloses a hybridoma cell line for secreting monoclonal antibody against rabies virus M protein and application thereof, relates to the field of biotechnology. A classification of the hybridoma cell line is named as hybridoma cell line 4A1, and the hybridoma cell line was deposited on Apr. 1, 2019 in the China Center for Type Culture Collection, Wuhan University, Wuhan, China, with a deposit number CCTCC NO: C201947. The monoclonal antibody prepared by the hybridoma cell line has high titer, good specificity and excellent biological characteristics. The present invention identifies the variant antigen epitope recognized by the RABV M protein, the hybridoma cell line can be used to distinguish Flury strain and other RABV strains, prepare kit for detecting rabies virus RABV, detect RABV infection and differential diagnosis vaccine Flury strain and other RABV strains.

Abstract: A method for detecting a human behavior includes: obtaining an image to be detected; obtaining a plurality of key points and a plurality of pieces of position information respectively corresponding to the plurality of key points by key-point recognition on the image to be detected; grouping the plurality of key points based on the plurality of pieces of position information to obtain a plurality of key-point groups, the plurality of key-point groups at least including a part of the plurality of key points; and determining a target human behavior based on key points in the plurality of key-point groups.

Abstract: A Lactobacillus paracasei and uses thereof. The Lactobacillus paracasei has a deposit number of CGMCC No. 14813. The Lactobacillus paracasei can be used for increasing the amount of an organic acid in a raw material. The Lactobacillus paracasei can be used for fermenting the raw material, where the raw material can be selected from at least one of fruits, which can increase the content of the organic acid in a fermented product.

Abstract: A reverse conducting lateral insulated-gate bipolar transistor includes a drift region formed on a substrate, a gate located on the drift region, an emitter region located on the drift region and close to one side of the gate, and a collector region located on the drift region and away from one side of the gate. Two or more N-well regions arranged at intervals are provided on the side of the drift region where the collector region is located. A P-well region is provided between the two or more N-well regions arranged at intervals; a P+ contact region is provided on the N-well region; an N+ contact region is provided on the P-well region; both the P+ contact region and the N+ contact region are conductively connected to a collector lead-out end.

Abstract: A transient voltage suppression device includes: a substrate; a first conductive type well region including a first well and a second well; a second conductive type well region including a third well and a fourth well, the third well being disposed between the first well and the second well so as to isolate the first well and the second well, and the second well being disposed between the third well and the fourth well; a zener diode active region; a first doped region, provided in the first well; a second doped region, provided in the first well; a third doped region, provided in the second well; a fourth doped region, provided in the second well; a fifth doped region, provided in the zener diode active region; and a sixth doped region, provided in the zener diode active region.

Abstract: A method, computer system, and computer program product for data monitoring management are provided. A first invalid zero value candidate from a data stream is received. A memory location for the first invalid zero value candidate is received. At a first time an access connection to the memory location is established. At a second time subsequent to the first time the access connection to the memory location is checked. Based on the checking, a determination is made whether the first invalid zero value candidate contains an invalid zero value.

Abstract: A diode and a manufacturing method therefor, and a semiconductor device. The diode includes: a substrate; an insulating buried layer provided on the substrate; a semiconductor layer provided on the insulating buried layer; anode; and a cathode, comprising: a trench-type contact, a trench being filled with a contact material, the trench extending from a first surface of the semiconductor layer to a second surface of the semiconductor layer, the first surface being a surface distant from the insulating buried layer, and the second surface being a surface facing the insulating buried layer; a cathode doped region surrounding the trench-type contact around and at the bottom of the trench-type contact, and also disposed on the first surface around the trench-type contact; and a negative electrode located on the cathode doped region and electrically connected to the cathode doped region.

Abstract: A method, computer system, and computer program product for data monitoring management are provided. A first invalid zero value candidate from a data stream is received. A memory location for the first invalid zero value candidate is received. At a first time an access connection to the memory location is established. At a second time subsequent to the first time the access connection to the memory location is checked. Based on the checking, a determination is made whether the first invalid zero value candidate contains an invalid zero value.

Abstract: A transient voltage suppression device and a manufacturing method therefor, the transient voltage suppression device including: a substrate, a first conductivity type well region and a second conductivity type well region disposed in the substrate. The first conductivity type well region includes a first well, a second well, and a third well. The second conductivity type well region includes a fourth well that isolates the first well from the second well, and a fifth well that isolates the second well from the third well. The device further includes a Zener diode well region provided in the first well, a first doped region provided in the Zener diode well region, a second doped region provided in the Zener diode well region, a third doped region provided in the second well, a fourth doped region provided in the third well, and a fifth doped region provided in the third well.

Abstract: Disclosed herein are de-bondable polyurethane adhesives based on thermally expandable microspheres, obtainable or obtained by the reaction of the components of (A) at least one di- or polyisocyanate, (B) at least one polyol, (C) catalyst, (D) thermally expandable microspheres, and (E) other additives, wherein the isocyanate index of the reaction is set in the range of from 28 to 65. Additionally disclosed herein is a method of using the de-bondable polyurethane adhesives for de-bonding metal and cutting pad during wafer cutting. Further disclosed herein is a method of using the de-bondable polyurethane adhesives in mechanical property testing sample preparation.

Abstract: A memory device includes a stack structure over a substrate, a channel structure extending in the stack structure, and a dielectric layer over the channel structure. The dielectric layer includes a first material. The memory device may also include a drain-select gate (DSG) cut structure extending through the dielectric layer. The DSG cut structure includes a second material different from the first material.

Abstract: Disclosed is a safety syringe that comprises a needle sleeve (1), a needle base (3) and a core rod (2). First claws (34) on the needle base (3) are configured to clamp in a first groove (111) on an inner wall of the needle sleeve (1), one of a proximal end of the needle base (3) and a distal end of the core rod (2) is provided with second claws (33), and the other one thereof is provided with a position-limiting member; the second claws (33) are configured to abut against the position-limiting member along a slanted surface.

Abstract: A transient voltage suppression device includes: a substrate; a first conductive type well region including a first well and a second well; a second conductive type well region including a third well and a fourth well, the third well being disposed between the first well and the second well so as to isolate the first well and the second well, and the second well being disposed between the third well and the fourth well; a zener diode active region; a first doped region, provided in the first well; a second doped region, provided in the first well; a third doped region, provided in the second well; a fourth doped region, provided in the second well; a fifth doped region, provided in the zener diode active region; and a sixth doped region, provided in the zener diode active region.

Abstract: Described herein is a method for joining a first metal pipe with a second metal pipe, the pipes being joined together in an overlapping area by use of a two-component polyurethane adhesive that encapsulates the overlapping area, where the method includes the steps of: (1) applying the two-component polyurethane adhesive onto an inner surface of a fixture; (2) inserting one end of the first metal pipe into one end of the second metal pipe so as to form a pipe assembly having the overlapping area between the two ends, and putting the overlapping area of the pipe assembly into the fixture; (3) closing the fixture such that the overlapping area of the pipe assembly is fixed in the fixture, and such that the adhesive therein encapsulates the overlapping area of the pipe assembly; (4) curing the two-component polyurethane adhesive; and (5) optionally, removing the fixture from the pipe assembly.

Abstract: An insulated gate bipolar transistor, comprising an anode second conductivity-type region and an anode first conductivity-type region provided on a drift region; the anode first conductivity-type region comprises a first region and a second region, and the anode second conductivity-type region comprises a third region and a fourth region, the dopant concentration of the first region being less than that of the second region, the dopant concentration of the third region being less than that of the fourth region, the third region being provided between the fourth region and a body region, the first region being provided below the fourth region, and the second region being provided below the third region and located between the first region and the body region.

Abstract: A TVS device and a manufacturing method therefor. The TVS device comprises: a first doping type semiconductor substrate (100); a second doping type deep well I (101), a second doping type deep well II (102), and a first doping type deep well (103) provided on the semiconductor substrate; a second doping type heavily doped region I (104) provided in the second doping type deep well I (101); a first doping type well region (105) and a first doping type heavily doped region I (106) provided in the second doping type deep well II (102); a first doping type heavily doped region II (107) and a second doping type heavily doped region II (108) provided in the first doping type deep well (105); a second doping type heavily doped region III (109) located in the first doping type well region (105) and the second doping type deep well II (102); and a first doping type doped region (110) provided in the first doping type well region (105).

Abstract: A trench gate depletion-type VDMOS device and a method for manufacturing the same are disclosed. The device comprises a drain region; a trench gate including a gate insulating layer on an inner wall of a trench and a gate electrode filled in the trench and surrounded by the gate insulating layer; a channel region located around the gate insulating layer; a well region located on both sides of the trench gate; a source regions located within the well region; a drift region located between the well region and the drain region; a second conductive-type doped region located between the channel region and the drain region; and a first conductive-type doped region located on both sides of the second conductive-type doped region and located between the drift region and the drain region.