Patents by Inventor Yan Gu

Yan Gu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12203346
    Abstract: The present invention disclosed a method for underground separation of components in sulfur-containing flue gas and sequestration of carbon dioxide and sulfides, comprising: injecting sulfur-containing flue gas into injection well which is arranged in a well pattern of a sequestrated aquifer in advance; transiting and injecting formation water into the formation at a first preset injection speed by injection well of the well pattern after injecting the sulfur-containing flue gas for a first preset time, maintaining the first formation pressure, and conducting water drainage and gas production by a production well of the well pattern in a mode of a fixed bottom hole flowing pressure; and determining the well shut-in time according to the nitrogen molar concentration of the production well and conducting well shut-in. The separated N2 is produced, while the separated CO2 and sulfides are sequestered in aquifer, achieving effective underground separation of the flue gas components.
    Type: Grant
    Filed: August 20, 2024
    Date of Patent: January 21, 2025
    Assignee: China University of Petroleum (East China)
    Inventors: Fuzhen Chen, Shengnan Wu, Shihao Liu, Yuhang Zhou, Yixuan Liu, Yan Tian, Jianwei Gu
  • Patent number: 12179004
    Abstract: Disclosed is a safety syringe that comprises a needle sleeve (1), a needle base (3) and a core rod (2). First claws (34) on the needle base (3) are configured to clamp in a first groove (111) on an inner wall of the needle sleeve (1), one of a proximal end of the needle base (3) and a distal end of the core rod (2) is provided with second claws (33), and the other one thereof is provided with a position-limiting member; the second claws (33) are configured to abut against the position-limiting member along a slanted surface.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: December 31, 2024
    Assignee: Shanghai Kindly Medical Instruments Co., Ltd.
    Inventors: Sen Lin, Dongke Liang, Hongxin Zhou, Lei Li, Peng Lin, Yan Gu
  • Patent number: 12119395
    Abstract: An insulated gate bipolar transistor, comprising an anode second conductivity-type region and an anode first conductivity-type region provided on a drift region; the anode first conductivity-type region comprises a first region and a second region, and the anode second conductivity-type region comprises a third region and a fourth region, the dopant concentration of the first region being less than that of the second region, the dopant concentration of the third region being less than that of the fourth region, the third region being provided between the fourth region and a body region, the first region being provided below the fourth region, and the second region being provided below the third region and located between the first region and the body region.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: October 15, 2024
    Assignees: SOUTHEAST UNIVERSITY, CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Long Zhang, Jie Ma, Yan Gu, Sen Zhang, Jing Zhu, Jinli Gong, Weifeng Sun, Longxing Shi
  • Publication number: 20240222478
    Abstract: A reverse conducting lateral insulated-gate bipolar transistor includes a drift region formed on a substrate, a gate located on the drift region, an emitter region located on the drift region and close to one side of the gate, and a collector region located on the drift region and away from one side of the gate. Two or more N-well regions arranged at intervals are provided on the side of the drift region where the collector region is located. A P-well region is provided between the two or more N-well regions arranged at intervals; a P+ contact region is provided on the N-well region; an N+ contact region is provided on the P-well region; both the P+ contact region and the N+ contact region are conductively connected to a collector lead-out end.
    Type: Application
    Filed: January 24, 2022
    Publication date: July 4, 2024
    Inventors: Sen ZHANG, Yan GU, Siyu CHEN
  • Patent number: 12015025
    Abstract: A transient voltage suppression device includes: a substrate; a first conductive type well region including a first well and a second well; a second conductive type well region including a third well and a fourth well, the third well being disposed between the first well and the second well so as to isolate the first well and the second well, and the second well being disposed between the third well and the fourth well; a zener diode active region; a first doped region, provided in the first well; a second doped region, provided in the first well; a third doped region, provided in the second well; a fourth doped region, provided in the second well; a fifth doped region, provided in the zener diode active region; and a sixth doped region, provided in the zener diode active region.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: June 18, 2024
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Shikang Cheng, Yan Gu, Sen Zhang
  • Publication number: 20240078149
    Abstract: A method, computer system, and computer program product for data monitoring management are provided. A first invalid zero value candidate from a data stream is received. A memory location for the first invalid zero value candidate is received. At a first time an access connection to the memory location is established. At a second time subsequent to the first time the access connection to the memory location is checked. Based on the checking, a determination is made whether the first invalid zero value candidate contains an invalid zero value.
    Type: Application
    Filed: September 7, 2022
    Publication date: March 7, 2024
    Inventors: Bo Chen Zhu, Cheng Fang Wang, Ai Ping Feng, Xinzhe Wang, Yan Ting Li, Hong Yan Gu
  • Publication number: 20240072178
    Abstract: A diode and a manufacturing method therefor, and a semiconductor device. The diode includes: a substrate; an insulating buried layer provided on the substrate; a semiconductor layer provided on the insulating buried layer; anode; and a cathode, comprising: a trench-type contact, a trench being filled with a contact material, the trench extending from a first surface of the semiconductor layer to a second surface of the semiconductor layer, the first surface being a surface distant from the insulating buried layer, and the second surface being a surface facing the insulating buried layer; a cathode doped region surrounding the trench-type contact around and at the bottom of the trench-type contact, and also disposed on the first surface around the trench-type contact; and a negative electrode located on the cathode doped region and electrically connected to the cathode doped region.
    Type: Application
    Filed: March 3, 2022
    Publication date: February 29, 2024
    Inventors: Yan GU, Hua SONG, Nailong HE, Sen ZHANG
  • Patent number: 11907051
    Abstract: A method, computer system, and computer program product for data monitoring management are provided. A first invalid zero value candidate from a data stream is received. A memory location for the first invalid zero value candidate is received. At a first time an access connection to the memory location is established. At a second time subsequent to the first time the access connection to the memory location is checked. Based on the checking, a determination is made whether the first invalid zero value candidate contains an invalid zero value.
    Type: Grant
    Filed: September 7, 2022
    Date of Patent: February 20, 2024
    Assignee: International Business Machines Corporation
    Inventors: Bo Chen Zhu, Cheng Fang Wang, Ai Ping Feng, Xinzhe Wang, Yan Ting Li, Hong Yan Gu
  • Patent number: 11887979
    Abstract: A transient voltage suppression device and a manufacturing method therefor, the transient voltage suppression device including: a substrate, a first conductivity type well region and a second conductivity type well region disposed in the substrate. The first conductivity type well region includes a first well, a second well, and a third well. The second conductivity type well region includes a fourth well that isolates the first well from the second well, and a fifth well that isolates the second well from the third well. The device further includes a Zener diode well region provided in the first well, a first doped region provided in the Zener diode well region, a second doped region provided in the Zener diode well region, a third doped region provided in the second well, a fourth doped region provided in the third well, and a fifth doped region provided in the third well.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: January 30, 2024
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Shikang Cheng, Yan Gu, Sen Zhang
  • Publication number: 20230407153
    Abstract: Disclosed herein are de-bondable polyurethane adhesives based on thermally expandable microspheres, obtainable or obtained by the reaction of the components of (A) at least one di- or polyisocyanate, (B) at least one polyol, (C) catalyst, (D) thermally expandable microspheres, and (E) other additives, wherein the isocyanate index of the reaction is set in the range of from 28 to 65. Additionally disclosed herein is a method of using the de-bondable polyurethane adhesives for de-bonding metal and cutting pad during wafer cutting. Further disclosed herein is a method of using the de-bondable polyurethane adhesives in mechanical property testing sample preparation.
    Type: Application
    Filed: September 7, 2021
    Publication date: December 21, 2023
    Inventors: Yuan Yan GU, Hong Tao SHAO, Hui GE, Li Ping WANG
  • Publication number: 20230189521
    Abstract: A memory device includes a stack structure over a substrate, a channel structure extending in the stack structure, and a dielectric layer over the channel structure. The dielectric layer includes a first material. The memory device may also include a drain-select gate (DSG) cut structure extending through the dielectric layer. The DSG cut structure includes a second material different from the first material.
    Type: Application
    Filed: January 4, 2022
    Publication date: June 15, 2023
    Inventors: Di Wang, Yan Gu, Zhiliang Xia, Wenxi Zhou, Zongliang Huo
  • Publication number: 20230146686
    Abstract: Disclosed is a safety syringe that comprises a needle sleeve (1), a needle base (3) and a core rod (2). First claws (34) on the needle base (3) are configured to clamp in a first groove (111) on an inner wall of the needle sleeve (1), one of a proximal end of the needle base (3) and a distal end of the core rod (2) is provided with second claws (33), and the other one thereof is provided with a position-limiting member; the second claws (33) are configured to abut against the position-limiting member along a slanted surface.
    Type: Application
    Filed: September 2, 2021
    Publication date: May 11, 2023
    Inventors: Sen Lin, Dongke Liang, Hongxin Zhou, Lei Li, Peng Li, Yan Gu
  • Publication number: 20230122120
    Abstract: A transient voltage suppression device includes: a substrate; a first conductive type well region including a first well and a second well; a second conductive type well region including a third well and a fourth well, the third well being disposed between the first well and the second well so as to isolate the first well and the second well, and the second well being disposed between the third well and the fourth well; a zener diode active region; a first doped region, provided in the first well; a second doped region, provided in the first well; a third doped region, provided in the second well; a fourth doped region, provided in the second well; a fifth doped region, provided in the zener diode active region; and a sixth doped region, provided in the zener diode active region.
    Type: Application
    Filed: August 15, 2019
    Publication date: April 20, 2023
    Inventors: Shikang Cheng, Yan Gu, Sen Zhang
  • Publication number: 20230021128
    Abstract: Described herein is a method for joining a first metal pipe with a second metal pipe, the pipes being joined together in an overlapping area by use of a two-component polyurethane adhesive that encapsulates the overlapping area, where the method includes the steps of: (1) applying the two-component polyurethane adhesive onto an inner surface of a fixture; (2) inserting one end of the first metal pipe into one end of the second metal pipe so as to form a pipe assembly having the overlapping area between the two ends, and putting the overlapping area of the pipe assembly into the fixture; (3) closing the fixture such that the overlapping area of the pipe assembly is fixed in the fixture, and such that the adhesive therein encapsulates the overlapping area of the pipe assembly; (4) curing the two-component polyurethane adhesive; and (5) optionally, removing the fixture from the pipe assembly.
    Type: Application
    Filed: December 9, 2020
    Publication date: January 19, 2023
    Inventors: YingHao Liu, Stefan Bokern, Xuyuan Peng-Poehler, Li Ping Wang, Yuan Yan Gu, Dong Liang, Yuan Fang
  • Publication number: 20220376094
    Abstract: An insulated gate bipolar transistor, comprising an anode second conductivity-type region and an anode first conductivity-type region provided on a drift region; the anode first conductivity-type region comprises a first region and a second region, and the anode second conductivity-type region comprises a third region and a fourth region, the dopant concentration of the first region being less than that of the second region, the dopant concentration of the third region being less than that of the fourth region, the third region being provided between the fourth region and a body region, the first region being provided below the fourth region, and the second region being provided below the third region and located between the first region and the body region.
    Type: Application
    Filed: August 26, 2020
    Publication date: November 24, 2022
    Inventors: Long ZHANG, Jie MA, Yan GU, Sen ZHANG, Jing ZHU, Jinli GONG, Weifeng SUN, Longxing SHI
  • Patent number: 11430780
    Abstract: A TVS device and a manufacturing method therefor. The TVS device comprises: a first doping type semiconductor substrate (100); a second doping type deep well I (101), a second doping type deep well II (102), and a first doping type deep well (103) provided on the semiconductor substrate; a second doping type heavily doped region I (104) provided in the second doping type deep well I (101); a first doping type well region (105) and a first doping type heavily doped region I (106) provided in the second doping type deep well II (102); a first doping type heavily doped region II (107) and a second doping type heavily doped region II (108) provided in the first doping type deep well (105); a second doping type heavily doped region III (109) located in the first doping type well region (105) and the second doping type deep well II (102); and a first doping type doped region (110) provided in the first doping type well region (105).
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: August 30, 2022
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Shikang Cheng, Yan Gu, Sen Zhang
  • Patent number: 11387349
    Abstract: A trench gate depletion-type VDMOS device and a method for manufacturing the same are disclosed. The device comprises a drain region; a trench gate including a gate insulating layer on an inner wall of a trench and a gate electrode filled in the trench and surrounded by the gate insulating layer; a channel region located around the gate insulating layer; a well region located on both sides of the trench gate; a source regions located within the well region; a drift region located between the well region and the drain region; a second conductive-type doped region located between the channel region and the drain region; and a first conductive-type doped region located on both sides of the second conductive-type doped region and located between the drift region and the drain region.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: July 12, 2022
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Yan Gu, Shikang Cheng, Sen Zhang
  • Patent number: 11276690
    Abstract: The present application provides an integrated semiconductor device and an electronic apparatus, comprising a semiconductor substrate and a first doped epitaxial layer having a first region, a second region, and a third region; a partition structure is arranged in the third region; the first region is formed having at least two second doped deep wells, and the second region is formed having at least two second doped deep wells; a dielectric island partially covers a region between two adjacent doped deep wells in the first region and second region; a gate structure covers the dielectric island; a first doped source region is located on the two sides of the gate structure, and a first doped source region located in the same second doped deep well is separated; a first doped trench is located on the two sides of the dielectric island in the first region, and extends laterally to the first doped source region.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: March 15, 2022
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Shikang Cheng, Yan Gu, Sen Zhang
  • Patent number: 11257720
    Abstract: A manufacturing method for a semiconductor device, and an integrated semiconductor device. The manufacturing method comprises: on a semiconductor substrate, forming an epitaxial layer having a first region, a second region, and a third region; forming at least one groove in the third region, forming at least two second doping deep traps in the first region, and forming at least two second doping deep traps in the second region; forming a first dielectric island between the second doping deep traps and forming a second dielectric island on the second doping deep traps; forming a first doping groove at both sides of the first dielectric island in the first region; forming a gate structure on the first dielectric island; forming an isolated first doping source region using the second dielectric island as a mask.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: February 22, 2022
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Shikang Cheng, Yan Gu, Sen Zhang
  • Patent number: 11233045
    Abstract: A transient voltage suppression device includes a substrate; a first conductivity type well region disposed in the substrate and comprising a first well and a second well; a third well disposed on the substrate, a bottom part of the third well extending to the substrate; a fourth well disposed in the first well; a first doped region disposed in the second well; a second doped region disposed in the third well; a third doped region disposed in the fourth well; a fourth doped region disposed in the fourth well; a fifth doped region extending from inside of the fourth well to the outside of the fourth well, a portion located outside the fourth well being located in the first well; a sixth doped region disposed in the first well; a seventh doped region disposed below the fifth doped region and in the first well.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: January 25, 2022
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Shikang Cheng, Yan Gu, Sen Zhang