Patents by Inventor Yan-Hao Chen

Yan-Hao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210376527
    Abstract: An electrical connection assembly and a floating connector are provided. The floating connector includes a floating module, a main body, and a plurality of elastic components. The floating module defines an active region therein, and the floating module has a plurality of thru-holes arranged outside of the active region. The main body is inserted into the active region of the floating module. The elastic components are disposed in the active region and are elastically deformable along an insertion direction. Two ends of each of the elastic components are respectively abutted against the floating module and the main body, so that the main body is movable along the insertion direction relative to the floating module through at least one of the elastic components.
    Type: Application
    Filed: September 24, 2020
    Publication date: December 2, 2021
    Inventors: heng-shan Cheng, yan Xu, CHUNG-NAN PAO, XUAN-HAO CHEN
  • Publication number: 20210376528
    Abstract: A connection device and a floating connection assembly are provided. The floating connection assembly includes a floating connector and an assembling module. The floating connector includes a floating module and a main body. The floating module defines an assembling region and a plurality of holding regions that are distributed around the assembling region. The main body is inserted into the assembling region of the floating module. The assembling module is retained by the floating module through the holding regions. The floating module and the assembling module are jointly configured to movably clamp a panel, and are jointly movable relative to the panel.
    Type: Application
    Filed: September 24, 2020
    Publication date: December 2, 2021
    Inventors: CHUNG-NAN PAO, heng-shan Cheng, XUAN-HAO CHEN, yan Xu
  • Patent number: 11113216
    Abstract: A multi-processor system handles interrupts using a power and performance status of each processor and a usage scenario of each processor. The power and performance status is indicated by factors that affect power consumption and processor performance. The system identifies one of the processors for handling an interrupt based on a weighted combination of the factors. Each factor is weighted based on a usage scenario for which the interrupt was generated. The system then dispatches the interrupt to the identified one of the processors.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: September 7, 2021
    Assignee: MediaTek Inc.
    Inventors: Chia-Hao Hsu, Sen-Yu Cheng, Yan-Ting Chen, Po-Kai Chi
  • Publication number: 20210175876
    Abstract: A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.
    Type: Application
    Filed: February 19, 2021
    Publication date: June 10, 2021
    Inventors: Po-Chia LAI, Meng-Hung SHEN, Chi-Lin LIU, Stefan RUSU, Yan-Hao CHEN, Jerry Chang-Jui KAO
  • Patent number: 10931264
    Abstract: A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chia Lai, Meng-Hung Shen, Chi-Lin Liu, Stefan Rusu, Yan-Hao Chen, Jerry Chang-Jui Kao
  • Publication number: 20210005633
    Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.
    Type: Application
    Filed: September 24, 2020
    Publication date: January 7, 2021
    Inventors: Wei-An Lai, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan, Yan-Hao Chen
  • Publication number: 20210005634
    Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.
    Type: Application
    Filed: September 24, 2020
    Publication date: January 7, 2021
    Inventors: Wei-An Lai, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan, Yan-Hao Chen
  • Patent number: 10797078
    Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wei-An Lai, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan, Yan-Hao Chen
  • Publication number: 20200058681
    Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.
    Type: Application
    Filed: August 14, 2018
    Publication date: February 20, 2020
    Inventors: Wei-An Lai, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan, Yan-Hao Chen
  • Publication number: 20190296719
    Abstract: A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.
    Type: Application
    Filed: June 11, 2019
    Publication date: September 26, 2019
    Inventors: Po-Chia LAI, Meng-Hung SHEN, Chi-Lin LIU, Stefan RUSU, Yan-Hao CHEN, Jerry Chang-Jui KAO
  • Patent number: 10326430
    Abstract: A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: June 18, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chia Lai, Meng-Hung Shen, Chi-Lin Liu, Stefan Rusu, Yan-Hao Chen, Jerry Chang-Jui Kao
  • Publication number: 20180152175
    Abstract: A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.
    Type: Application
    Filed: April 12, 2017
    Publication date: May 31, 2018
    Inventors: Po-Chia LAI, Meng-Hung Shen, Chi-Lin Liu, Stefan Rusu, Yan-Hao Chen, Jerry Chang-Jui Kao
  • Patent number: 8859311
    Abstract: A flip-chip light-emitting diode structure comprises a carrier substrate, a light-emitting die structure, a reflective layer, an aperture, a dielectric layer, a first contact layer and a second contact layer. The light-emitting die structure, located on the carrier substrate, comprises a first type semiconductor layer, a second type semiconductor layer and a light emitting layer. The light emitting layer is formed between the first type and the second type semiconductor layer. The reflective layer is located on the first type semiconductor layer. The aperture penetrates the light-emitting die structure. The dielectric layer covers an inner sidewall of the aperture and extends to a portion of a surface of the reflective layer. The first contact layer is disposed on the part of the reflective layer not covered by the dielectric layer. The second contact layer fills up the aperture and is electrically connected to the second type semiconductor layer.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: October 14, 2014
    Assignee: Lextar Electronics Corporation
    Inventors: Chia-En Lee, Yan-Hao Chen
  • Publication number: 20140061700
    Abstract: A flip-chip light-emitting diode structure comprises a carrier substrate, a light-emitting die structure, a reflective layer, an aperture, a dielectric layer, a first contact layer and a second contact layer. The light-emitting die structure, located on the carrier substrate, comprises a first type semiconductor layer, a second type semiconductor layer and a light emitting layer. The light emitting layer is formed between the first type and the second type semiconductor layer. The reflective layer is located on the first type semiconductor layer. The aperture penetrates the light-emitting die structure. The dielectric layer covers an inner sidewall of the aperture and extends to a portion of a surface of the reflective layer. The first contact layer is disposed on the part of the reflective layer not covered by the dielectric layer. The second contact layer fills up the aperture and is electrically connected to the second type semiconductor layer.
    Type: Application
    Filed: August 13, 2013
    Publication date: March 6, 2014
    Applicant: Lextar Electronics Corporation
    Inventors: Chia-En Lee, Yan-Hao Chen