Abstract: In a management method and system for a shared radio unit and a computer-readable storage medium, N user groups are created for N operators, where N is a positive integer greater than 1; resources of the shared radio unit are divided into public resources and N private resources; the N user groups and the N private resources are bound correspondingly, and the N user groups are set to only have access to corresponding private resources bound in the N private resources; resource permissions of the shared radio unit are initialized, and account passwords configured for the N user groups are sent to the corresponding N operators respectively; and the N operators configures parameters to a data model language database according to the account passwords.

Abstract: In a method for unlocking a screen of a mobile device, at least one user-specific number is set and stored into a storage unit of the mobile device. The user-specific number is read from the storage unit and displayed on the screen for selection by a user, when the screen is locked because of input of a wrong password. An unlocking request is transmitted to a terminal providing the selected user-specific number. The mobile device communicates with the terminal, and receives a confirmation message from the terminal, and the screen is unlocked according to the confirmation message.

Abstract: In a method for unlocking a screen of a mobile device, at least one user-specific number is set and stored into a storage unit of the mobile device. The user-specific number is read from the storage unit and displayed on the screen for selection by a user, when the screen is locked because of input of a wrong password. An unlocking request is transmitted to a terminal providing the selected user-specific number. The mobile device communicates with the terminal, and receives a confirmation message from the terminal, and the screen is unlocked according to the confirmation message.

Abstract: An electrostatic discharge (ESD) protection apparatus includes at least one first transistor and at least one second transistor. The first transistor includes a control terminal, a first terminal, a second terminal, and a bulk. The control terminal and the second terminal of the first transistor are coupled to each other. The first terminal of the first transistor is coupled to one of a pad and a power rail line. Likewise, the second transistor also includes a control terminal, a first terminal, and a second terminal. The first terminal of the second transistor is coupled to the bulk of the first transistor, the bulk of the second transistor is coupled to the second terminal of the first transistor, and the second terminal of the second transistor is coupled to the other of the pad and the power rail line.

Abstract: ESD protection circuit including a resistor and at least one protection transistor; the resistor coupled between an I/O signal node and an internal node of internal circuit, the protection transistors serially coupled between the internal node and a voltage node with each protection transistor comprising a gate and a drain which is coupled to the gate.

Abstract: Electrostatic discharge (ESD) protection circuit including a first silicon controlled rectifier (SCR) and a trigger circuit; the trigger circuit including a first MOS transistor and a second transistor, triggering the first SCR and providing a second SCR shunt with the first SCR during ESD.

Abstract: An electrostatic discharge (ESD) protection apparatus includes at least one first transistor and at least one second transistor. The first transistor includes a control terminal, a first terminal, a second terminal, and a bulk. The control terminal and the second terminal of the first transistor are coupled to each other. The first terminal of the first transistor is coupled to one of a pad and a power rail line. Likewise, the second transistor also includes a control terminal, a first terminal, and a second terminal. The first terminal of the second transistor is coupled to the bulk of the first transistor, the bulk of the second transistor is coupled to the second terminal of the first transistor, and the second terminal of the second transistor is coupled to the other of the pad and the power rail line.

Abstract: ESD protection circuit including a resistor and at least one protection transistor; the resistor coupled between an I/O signal node and an internal node of internal circuit, the protection transistors serially coupled between the internal node and a voltage node with each protection transistor comprising a gate and a drain which is coupled to the gate.

Abstract: Electrostatic discharge (ESD) protection circuit including a first silicon controlled rectifier (SCR) and a trigger circuit; the trigger circuit including a first MOS transistor and a second transistor, triggering the first SCR and providing a second SCR shunt with the first SCR during ESD.

Abstract: A bandgap reference circuit includes a reference current generator for respectively generating a first reference current on a first current path and a second reference current on a second current path, a current mirror for generating a third reference current on a third current path based on the first and second reference currents, an operation amplifier for rendering the first reference current substantially identical to the second reference current and a feedback circuit for rendering a node voltage on the first current path substantially identical to another node voltage on the third current path, so as to eliminate possible errors caused by a channel length modulation effect in the current mirror.

Abstract: A bandgap reference circuit comprises: a current generator for generating an output current, the current generator comprising a first reference unit and a plurality of second reference units arranged in parallel, where the current generator is capable of determining the magnitude of the output current according to the reference units; a first resistor, coupled between a first terminal of the first reference unit and a node, for transmitting a first current; a second resistor, coupled to the node and a first terminal of each second reference unit, for transmitting a second current; a third resistor, coupled between the node and an output terminal of the bandgap reference circuit, for transmitting a third current; and a current-to-voltage converter, coupled to the third resistor, for generating a bandgap voltage according to the output current and the third current.

Abstract: A multi-band VCO module includes a multi-band VCO and a controlling module. The multi-band VCO is for selecting a specific band from a plurality of bands according to a band selecting signal, and for outputting an oscillating signal according to a predetermined voltage and the specific band. The controlling module, coupled to the multi-band VCO, is for setting the band selecting signal according to a reference frequency of the reference signal and an oscillating frequency of the oscillating signal. A related method and a PLL circuit utilizing the multi-band VCO module are also disclosed.

Abstract: A signal routing method adapted to a DWA structure is provided. The signal routing method at least includes following steps. An M-bit input digital signal is provided. The odd bit in the input digital signal is routed into a low-bit signal of an output digital signal, and the even bit in the input digital signal is routed into a high-bit signal of the output digital signal, wherein the output digital signal has M bits.

Abstract: A bandgap reference circuit includes an input circuit having a first FET, a second FET, and a first resistor, wherein a first node is connected to the first FET having a first threshold voltage, the first resistor is connected between a second node and the second FET having a second threshold voltage; a mirroring circuit for controlling two output currents respectively derived from the first and second nodes, and maintaining the two output currents to a specific current ratio; and an operation amplifier connected to the first node, the second node of the input circuit, and the mirroring circuit, for controlling two voltages respectively at the first and second nodes of the input circuit to a specific voltage ratio; wherein the first FET and the second FET are both operating in the subthreshold region, the first threshold voltage is larger than the second threshold voltage, and the two output currents are independent of temperature.

Abstract: A bandgap reference circuit includes a PTAT current generating circuit for generating a PTAT current; a CTAT circuit generating circuit for generating a CTAT current; a node for receiving the PTAT current and the CTAT current; and, a first resistor connected between the node and a ground, wherein a reference voltage is derived from the first resistor when a superposed current of the PTAT current and the CTAT current is flowing through the first resistor.

Abstract: A data weighted average (DWA) structure including a first delay unit, a binary to thermometer code converter, an adder, a second delay unit, a decoder, a barrel shifter, and a plurality of signal lines is provided. The first delay unit delays an input digital signal. The binary to thermometer code converter converts an output signal of the first delay unit into a thermal code. The second delay unit delays an output signal of the adder. The adder adds the input digital signal to an output signal of the second delay unit. The decoder decodes the output signal of the second delay unit. The barrel shifter generates an output signal from the thermal code in accordance with an output signal of the decoder. The signal lines route the output signal of the barrel shifter into two independent control signal groups.

Abstract: A data weighted average (DWA) structure including a first delay unit, a binary to thermometer code converter, an adder, a second delay unit, a decoder, a barrel shifter, and a plurality of signal lines is provided. The first delay unit delays an input digital signal. The binary to thermometer code converter converts an output signal of the first delay unit into a thermal code. The second delay unit delays an output signal of the adder. The adder adds the input digital signal to an output signal of the second delay unit. The decoder decodes the output signal of the second delay unit. The barrel shifter generates an output signal from the thermal code in accordance with an output signal of the decoder. The signal lines route the output signal of the barrel shifter into two independent control signal groups.

Abstract: A bandgap reference circuit comprises: a current generator for generating an output current, the current generator comprising a first reference unit and a plurality of second reference units arranged in parallel, where the current generator is capable of determining the magnitude of the output current according to the reference units; a first resistor, coupled between a first terminal of the first reference unit and a node, for transmitting a first current; a second resistor, coupled to the node and a first terminal of each second reference unit, for transmitting a second current; a third resistor, coupled between the node and an output terminal of the bandgap reference circuit, for transmitting a third current; and a current-to-voltage converter, coupled to the third resistor, for generating a bandgap voltage according to the output current and the third current.

Abstract: A bandgap reference circuit includes a reference current generator for respectively generating a first reference current on a first current path and a second reference current on a second current path, a current mirror for generating a third reference current on a third current path based on the first and second reference currents, an operation amplifier for rendering the first reference current substantially identical to the second reference current and a feedback circuit for rendering a node voltage on the first current path substantially identical to another node voltage on the third current path, so as to eliminate possible errors caused by a channel length modulation effect in the current mirror.

Abstract: A supply-independent biasing circuit applied to a bandgap reference circuit or a proportional to absolute temperature (PTAT) current generating circuit. The bandgap reference circuit or the PTAT current generating circuit includes a mirroring circuit, an operation amplifier, and an input circuit. The mirroring circuit including a plurality of first type FETs. The operation amplifier includes a first type FET connecting to a current input terminal of the operation amplifier. And, the supply-independent biasing circuit includes a first type FET having a gate connected to gates of the first type FETs in the mirroring circuit and having a drain acted as an output current path; and, a current mirror including a plurality of second type FETs and having a current receiving terminal connected to the output current path and having a current outputting terminal connected to the current input terminal of the operation amplifier.