Abstract: A one time programmable memory including a substrate, a plurality of isolation structures, a first transistor, and a second transistor is provided. The isolation structures are disposed in the substrate for defining an active area. A recess is formed on each of the isolation structures so that the top surface of the isolation structure is lower than that of the substrate. The first transistor is disposed on the active area of the substrate and is extended to the sidewall of the recess. The gate of the first transistor is a select gate. The second transistor is disposed on the active area of the substrate and is connected to the first transistor in series. The gate of the second transistor is a floating gate which is disposed across the substrate between the isolation structures in blocks and is extended to the sidewall of the recess.

Abstract: A method of manufacturing a non-volatile memory includes providing a substrate and forming a patterned mask layer, a tunnel dielectric layer, and a first conductive layer on the substrate. The first conductive layer on the mask layer is removed to form second conductive layers disposed on the sidewall of the mask layer and the substrate. The mask layer is then removed and a source region is formed. Subsequently, an inter-gate dielectric layer and a third conductive layer are formed on the substrate. The third conductive layer is patterned to cover the source region and a portion of the second conductive layer on both sides of the source region. A portion of the inter-gate dielectric layer and the second conductive layers are then removed. After that, a dielectric layer, a fourth conductive layer, and a drain region are formed, respectively.

Abstract: A non-volatile memory is provided, including a substrate, a control gate, a floating gate, and a select gate. A source region and a drain region are disposed in the substrate. The control gate is disposed on the substrate between the source region and the drain region. The floating gate is disposed between the control gate and the substrate. The cross-section of the floating gate presents, for example, an L-shape and the floating gate includes a central region which is perpendicular to the substrate and a lateral region which is parallel to the substrate. The central region is adjacent to the source region. The select gate is disposed on the sidewall of the control gate and the lateral region of the floating gate, and is adjacent to the drain region. Besides, the present invention further includes a method of manufacturing the above non-volatile memory.

Abstract: A non-volatile memory is provided, including a substrate, a control gate, a floating gate, and a select gate. A source region and a drain region are disposed in the substrate. The control gate is disposed on the substrate between the source region and the drain region. The floating gate is disposed between the control gate and the substrate. The cross-section of the floating gate presents, for example, an L-shape and the floating gate includes a central region which is perpendicular to the substrate and a lateral region which is parallel to the substrate. The central region is adjacent to the source region. The select gate is disposed on the sidewall of the control gate and the lateral region of the floating gate, and is adjacent to the drain region. Besides, the present invention further includes a method of manufacturing the above non-volatile memory.

Abstract: A one time programmable memory including a substrate, a plurality of isolation structures, a first transistor, and a second transistor is provided. The isolation structures are disposed in the substrate for defining an active area. A recess is formed on each of the isolation structures so that the top surface of the isolation structure is lower than that of the substrate. The first transistor is disposed on the active area of the substrate and is extended to the sidewall of the recess. The gate of the first transistor is a select gate. The second transistor is disposed on the active area of the substrate and is connected to the first transistor in series. The gate of the second transistor is a floating gate which is disposed across the substrate between the isolation structures in blocks and is extended to the sidewall of the recess.