Abstract: Circuits for a multiplier with a built-in accumulator and a method of performing multiplication with accumulation are disclosed. An embodiment of the disclosed circuits includes a logic circuit coupled to receive two inputs. The logic circuit is capable of generating a plurality of value bits from the inputs received. In one embodiment, the logic circuit includes a Booth recoder circuit that generates a plurality of partial products. A block of adders is coupled to logic circuit to receive and sum up the value bits. An adder adds the summation result from the block of adders to a previous accumulated value to generate intermediate sum and carry values. An accumulator, coupled to the adder, receives and stores the intermediate values.