Patents by Inventor Yan-Jou Chen
Yan-Jou Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11903325Abstract: A memory device includes a substrate; an active area extending along a first direction on the substrate; a gate line traversing the active area and extending along a second direction that is not parallel to the first direction; a source doped region in the active area and on a first side of the gate line; a main source line extending along the first direction; a source line extension coupled to the main source line and extending along the second direction; a drain doped region in the active area and on a second side of the gate line that is opposite to the first side; and a data storage element electrically coupled to the drain doped region. The main source line is electrically connected to the source doped region via the source line extension.Type: GrantFiled: May 2, 2022Date of Patent: February 13, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Ting Wu, Yan-Jou Chen, Cheng-Tung Huang, Jen-Yu Wang, Po-Chun Yang, Yung-Ching Hsieh, Jian-Jhong Chen, Bo-Chang Li
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Patent number: 11699705Abstract: A semiconductor device includes a PMOS region and a NMOS region on a substrate, a first fin-shaped structure on the PMOS region, a first single diffusion break (SDB) structure in the first fin-shaped structure, a first gate structure on the first SDB structure, and a second gate structure on the first fin-shaped structure. Preferably, the first gate structure and the second gate structure are of different materials and the first gate structure disposed directly on top of the first SDB structure is a polysilicon gate while the second gate structure disposed on the first fin-shaped structure is a metal gate in the PMOS region.Type: GrantFiled: February 22, 2022Date of Patent: July 11, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yen-Wei Tung, Jen-Yu Wang, Cheng-Tung Huang, Yan-Jou Chen
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Patent number: 11637103Abstract: A semiconductor device includes a PMOS region and a NMOS region on a substrate, a first fin-shaped structure on the PMOS region, a first single diffusion break (SDB) structure in the first fin-shaped structure, a first gate structure on the first SDB structure, and a second gate structure on the first fin-shaped structure. Preferably, the first gate structure and the second gate structure are of different materials and the first gate structure disposed directly on top of the first SDB structure is a polysilicon gate while the second gate structure disposed on the first fin-shaped structure is a metal gate in the PMOS region.Type: GrantFiled: October 4, 2021Date of Patent: April 25, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yen-Wei Tung, Jen-Yu Wang, Cheng-Tung Huang, Yan-Jou Chen
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Publication number: 20220263012Abstract: A memory device includes a substrate; an active area extending along a first direction on the substrate; a gate line traversing the active area and extending along a second direction that is not parallel to the first direction; a source doped region in the active area and on a first side of the gate line; a main source line extending along the first direction; a source line extension coupled to the main source line and extending along the second direction; a drain doped region in the active area and on a second side of the gate line that is opposite to the first side; and a data storage element electrically coupled to the drain doped region. The main source line is electrically connected to the source doped region via the source line extension.Type: ApplicationFiled: May 2, 2022Publication date: August 18, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yi-Ting Wu, Yan-Jou Chen, Cheng-Tung Huang, Jen-Yu Wang, Po-Chun Yang, Yung-Ching Hsieh, Jian-Jhong Chen, Bo-Chang Li
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Publication number: 20220181324Abstract: A semiconductor device includes a PMOS region and a NMOS region on a substrate, a first fin-shaped structure on the PMOS region, a first single diffusion break (SDB) structure in the first fin-shaped structure, a first gate structure on the first SDB structure, and a second gate structure on the first fin-shaped structure. Preferably, the first gate structure and the second gate structure are of different materials and the first gate structure disposed directly on top of the first SDB structure is a polysilicon gate while the second gate structure disposed on the first fin-shaped structure is a metal gate in the PMOS region.Type: ApplicationFiled: February 22, 2022Publication date: June 9, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yen-Wei Tung, Jen-Yu Wang, Cheng-Tung Huang, Yan-Jou Chen
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Patent number: 11355695Abstract: A memory device includes a substrate; an active area extending along a first direction on the substrate; a gate line traversing the active area and extending along a second direction that is not parallel to the first direction; a source doped region in the active area and on a first side of the gate line; a main source line extending along the first direction; a source line extension coupled to the main source line and extending along the second direction; a drain doped region in the active area and on a second side of the gate line that is opposite to the first side; and a data storage element electrically coupled to the drain doped region. The main source line is electrically connected to the source doped region via the source line extension.Type: GrantFiled: April 19, 2020Date of Patent: June 7, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Ting Wu, Yan-Jou Chen, Cheng-Tung Huang, Jen-Yu Wang, Po-Chun Yang, Yung-Ching Hsieh, Jian-Jhong Chen, Bo-Chang Li
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Publication number: 20220020745Abstract: A semiconductor device includes a PMOS region and a NMOS region on a substrate, a first fin-shaped structure on the PMOS region, a first single diffusion break (SDB) structure in the first fin-shaped structure, a first gate structure on the first SDB structure, and a second gate structure on the first fin-shaped structure. Preferably, the first gate structure and the second gate structure are of different materials and the first gate structure disposed directly on top of the first SDB structure is a polysilicon gate while the second gate structure disposed on the first fin-shaped structure is a metal gate in the PMOS region.Type: ApplicationFiled: October 4, 2021Publication date: January 20, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yen-Wei Tung, Jen-Yu Wang, Cheng-Tung Huang, Yan-Jou Chen
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Patent number: 11171137Abstract: A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a first single diffusion break (SDB) structure in the first fin-shaped structure; forming a first gate structure on the first SDB structure and a second gate structure on the first fin-shaped structure; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned mask on the first gate structure; and performing a replacement metal gate (RMG) process to transform the second gate structure into a metal gate.Type: GrantFiled: October 6, 2019Date of Patent: November 9, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yen-Wei Tung, Jen-Yu Wang, Cheng-Tung Huang, Yan-Jou Chen
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Publication number: 20210313509Abstract: A memory device includes a substrate; an active area extending along a first direction on the substrate; a gate line traversing the active area and extending along a second direction that is not parallel to the first direction; a source doped region in the active area and on a first side of the gate line; a main source line extending along the first direction; a source line extension coupled to the main source line and extending along the second direction; a drain doped region in the active area and on a second side of the gate line that is opposite to the first side; and a data storage element electrically coupled to the drain doped region. The main source line is electrically connected to the source doped region via the source line extension.Type: ApplicationFiled: April 19, 2020Publication date: October 7, 2021Inventors: Yi-Ting Wu, Yan-Jou Chen, Cheng-Tung Huang, Jen-Yu Wang, Po-Chun Yang, Yung-Ching Hsieh, Jian-Jhong Chen, Bo-Chang Li
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Publication number: 20200035680Abstract: A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a first single diffusion break (SDB) structure in the first fin-shaped structure; forming a first gate structure on the first SDB structure and a second gate structure on the first fin-shaped structure; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned mask on the first gate structure; and performing a replacement metal gate (RMG) process to transform the second gate structure into a metal gate.Type: ApplicationFiled: October 6, 2019Publication date: January 30, 2020Inventors: Yen-Wei Tung, Jen-Yu Wang, Cheng-Tung Huang, Yan-Jou Chen
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Patent number: 10483264Abstract: A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a first single diffusion break (SDB) structure in the first fin-shaped structure; forming a first gate structure on the first SDB structure and a second gate structure on the first fin-shaped structure; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned mask on the first gate structure; and performing a replacement metal gate (RMG) process to transform the second gate structure into a metal gate.Type: GrantFiled: July 27, 2017Date of Patent: November 19, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yen-Wei Tung, Jen-Yu Wang, Cheng-Tung Huang, Yan-Jou Chen
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Publication number: 20190006360Abstract: A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a first single diffusion break (SDB) structure in the first fin-shaped structure; forming a first gate structure on the first SDB structure and a second gate structure on the first fin-shaped structure; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned mask on the first gate structure; and performing a replacement metal gate (RMG) process to transform the second gate structure into a metal gate.Type: ApplicationFiled: July 27, 2017Publication date: January 3, 2019Inventors: Yen-Wei Tung, Jen-Yu Wang, Cheng-Tung Huang, Yan-Jou Chen
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Patent number: 8723776Abstract: A gate driving circuit receives a plurality of clock signals in a sequence and includes a plurality of cascaded drive units sequentially outputting an output signal, wherein a first-stage drive unit of the gate driving circuit receives a scan start signal or a scan end signal while a last-stage drive unit thereof receives a scan end signal or a scan start signal; wherein a driving direction of the gate driving circuit is reversed by reversing the sequence of the clock signals and exchanging the scan start signal and the scan end signal. The present invention further provides a driving method of a gate driving circuit.Type: GrantFiled: June 20, 2012Date of Patent: May 13, 2014Assignee: Hannstar Display Corp.Inventors: Hsien Cheng Chang, Yan Jou Chen
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Patent number: 8305329Abstract: An integrated gate driver circuit receives a plurality of clocks and includes a plurality of driving units cascaded in series. Each driving unit is for driving a load and includes an input terminal, an output terminal, a first switch and a second switch. The first switch has a first terminal coupled to the input terminal, a second terminal coupled to a first node, and a control terminal receiving a first clock, and the first switch is turned on when the first clock is at high level. The second switch has a first terminal receiving a second clock, a second terminal coupled to the output terminal, and a control terminal coupled to the first node, wherein the second clock charges and discharges the load through the second switch when the first node is at high level; wherein the output terminal of each driving unit is coupled to the input terminal of the immediately succeeding driving unit.Type: GrantFiled: September 16, 2009Date of Patent: November 6, 2012Assignee: HannStar Display Corp.Inventors: Yan Jou Chen, Yung Hsin Lu, Chia Hua Yu, Sung Chun Lin
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Patent number: 8300002Abstract: A gate driving circuit receives a plurality of clock signals in a sequence and includes a plurality of cascaded drive units sequentially outputting an output signal, wherein a first-stage drive unit of the gate driving circuit receives a scan start signal or a scan end signal while a last-stage drive unit thereof receives a scan end signal or a scan start signal; wherein a driving direction of the gate driving circuit is reversed by reversing the sequence of the clock signals and exchanging the scan start signal and the scan end signal. The present invention further provides a driving method of a gate driving circuit.Type: GrantFiled: April 1, 2010Date of Patent: October 30, 2012Assignee: Hannstar Display Corp.Inventors: Hsien Cheng Chang, Yan Jou Chen
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Patent number: 8299821Abstract: An integrated gate driver circuit includes an output drive circuit and a voltage stabilizing circuit. The voltage stabilizing circuit is configured to stabilize an output voltage outputted by the output drive circuit thereby reducing the ripple of the output voltage.Type: GrantFiled: May 18, 2010Date of Patent: October 30, 2012Assignee: Hannstar Display Corp.Inventors: Yan Jou Chen, Hsien Cheng Chang
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Publication number: 20120256899Abstract: A gate driving circuit receives a plurality of clock signals in a sequence and includes a plurality of cascaded drive units sequentially outputting an output signal, wherein a first-stage drive unit of the gate driving circuit receives a scan start signal or a scan end signal while a last-stage drive unit thereof receives a scan end signal or a scan start signal; wherein a driving direction of the gate driving circuit is reversed by reversing the sequence of the clock signals and exchanging the scan start signal and the scan end signal. The present invention further provides a driving method of a gate driving circuit.Type: ApplicationFiled: June 20, 2012Publication date: October 11, 2012Applicant: HANNSTAR DISPLAY CORP.Inventors: Hsien Cheng CHANG, Yan Jou CHEN
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Patent number: 8072411Abstract: A gate line driving circuit comprises a driving chip comprising first and second output ports, a LCD panel comprising first, second and third gate lines, a first switch and a second switch. Two terminals of the first gate line are respectively connected to the first output port and the control terminal of the first switch. Two terminals of the third gate line are respectively connected to the second output port and the control terminal of the second switch. The input terminal of the first switch electrically connects an operating voltage and the output terminal of the first switch electrically connects to the input terminal of the second switch. The output terminal of the second switch electrically connects a ground point, and one terminal of the second gate line is connected to between the output terminal of the first switch and the input terminal of the second switch.Type: GrantFiled: July 13, 2009Date of Patent: December 6, 2011Assignee: Hannstar Display Corp.Inventors: Yan-Jou Chen, Hung-Jen Wang
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Publication number: 20100289535Abstract: An integrated gate driver circuit includes an output drive circuit and a voltage stabilizing circuit. The voltage stabilizing circuit is configured to stabilize an output voltage outputted by the output drive circuit thereby reducing the ripple of the output voltage.Type: ApplicationFiled: May 18, 2010Publication date: November 18, 2010Applicant: HANNSTAR DISPLAY CORP.Inventors: Yan Jou CHEN, Hsien Cheng CHANG
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Publication number: 20100259530Abstract: A gate driving circuit receives a plurality of clock signals in a sequence and includes a plurality of cascaded drive units sequentially outputting an output signal, wherein a first-stage drive unit of the gate driving circuit receives a scan start signal or a scan end signal while a last-stage drive unit thereof receives a scan end signal or a scan start signal; wherein a driving direction of the gate driving circuit is reversed by reversing the sequence of the clock signals and exchanging the scan start signal and the scan end signal. The present invention further provides a driving method of a gate driving circuit.Type: ApplicationFiled: April 1, 2010Publication date: October 14, 2010Applicant: HANNSTAR DISPLAY CORP.Inventors: Hsien Cheng CHANG, Yan Jou CHEN