Patents by Inventor Yan-Jou Chen

Yan-Jou Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10483264
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a first single diffusion break (SDB) structure in the first fin-shaped structure; forming a first gate structure on the first SDB structure and a second gate structure on the first fin-shaped structure; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned mask on the first gate structure; and performing a replacement metal gate (RMG) process to transform the second gate structure into a metal gate.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: November 19, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Wei Tung, Jen-Yu Wang, Cheng-Tung Huang, Yan-Jou Chen
  • Publication number: 20190006360
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a first single diffusion break (SDB) structure in the first fin-shaped structure; forming a first gate structure on the first SDB structure and a second gate structure on the first fin-shaped structure; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned mask on the first gate structure; and performing a replacement metal gate (RMG) process to transform the second gate structure into a metal gate.
    Type: Application
    Filed: July 27, 2017
    Publication date: January 3, 2019
    Inventors: Yen-Wei Tung, Jen-Yu Wang, Cheng-Tung Huang, Yan-Jou Chen
  • Patent number: 8723776
    Abstract: A gate driving circuit receives a plurality of clock signals in a sequence and includes a plurality of cascaded drive units sequentially outputting an output signal, wherein a first-stage drive unit of the gate driving circuit receives a scan start signal or a scan end signal while a last-stage drive unit thereof receives a scan end signal or a scan start signal; wherein a driving direction of the gate driving circuit is reversed by reversing the sequence of the clock signals and exchanging the scan start signal and the scan end signal. The present invention further provides a driving method of a gate driving circuit.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: May 13, 2014
    Assignee: Hannstar Display Corp.
    Inventors: Hsien Cheng Chang, Yan Jou Chen
  • Patent number: 8305329
    Abstract: An integrated gate driver circuit receives a plurality of clocks and includes a plurality of driving units cascaded in series. Each driving unit is for driving a load and includes an input terminal, an output terminal, a first switch and a second switch. The first switch has a first terminal coupled to the input terminal, a second terminal coupled to a first node, and a control terminal receiving a first clock, and the first switch is turned on when the first clock is at high level. The second switch has a first terminal receiving a second clock, a second terminal coupled to the output terminal, and a control terminal coupled to the first node, wherein the second clock charges and discharges the load through the second switch when the first node is at high level; wherein the output terminal of each driving unit is coupled to the input terminal of the immediately succeeding driving unit.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: November 6, 2012
    Assignee: HannStar Display Corp.
    Inventors: Yan Jou Chen, Yung Hsin Lu, Chia Hua Yu, Sung Chun Lin
  • Patent number: 8300002
    Abstract: A gate driving circuit receives a plurality of clock signals in a sequence and includes a plurality of cascaded drive units sequentially outputting an output signal, wherein a first-stage drive unit of the gate driving circuit receives a scan start signal or a scan end signal while a last-stage drive unit thereof receives a scan end signal or a scan start signal; wherein a driving direction of the gate driving circuit is reversed by reversing the sequence of the clock signals and exchanging the scan start signal and the scan end signal. The present invention further provides a driving method of a gate driving circuit.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: October 30, 2012
    Assignee: Hannstar Display Corp.
    Inventors: Hsien Cheng Chang, Yan Jou Chen
  • Patent number: 8299821
    Abstract: An integrated gate driver circuit includes an output drive circuit and a voltage stabilizing circuit. The voltage stabilizing circuit is configured to stabilize an output voltage outputted by the output drive circuit thereby reducing the ripple of the output voltage.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: October 30, 2012
    Assignee: Hannstar Display Corp.
    Inventors: Yan Jou Chen, Hsien Cheng Chang
  • Publication number: 20120256899
    Abstract: A gate driving circuit receives a plurality of clock signals in a sequence and includes a plurality of cascaded drive units sequentially outputting an output signal, wherein a first-stage drive unit of the gate driving circuit receives a scan start signal or a scan end signal while a last-stage drive unit thereof receives a scan end signal or a scan start signal; wherein a driving direction of the gate driving circuit is reversed by reversing the sequence of the clock signals and exchanging the scan start signal and the scan end signal. The present invention further provides a driving method of a gate driving circuit.
    Type: Application
    Filed: June 20, 2012
    Publication date: October 11, 2012
    Applicant: HANNSTAR DISPLAY CORP.
    Inventors: Hsien Cheng CHANG, Yan Jou CHEN
  • Patent number: 8072411
    Abstract: A gate line driving circuit comprises a driving chip comprising first and second output ports, a LCD panel comprising first, second and third gate lines, a first switch and a second switch. Two terminals of the first gate line are respectively connected to the first output port and the control terminal of the first switch. Two terminals of the third gate line are respectively connected to the second output port and the control terminal of the second switch. The input terminal of the first switch electrically connects an operating voltage and the output terminal of the first switch electrically connects to the input terminal of the second switch. The output terminal of the second switch electrically connects a ground point, and one terminal of the second gate line is connected to between the output terminal of the first switch and the input terminal of the second switch.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: December 6, 2011
    Assignee: Hannstar Display Corp.
    Inventors: Yan-Jou Chen, Hung-Jen Wang
  • Publication number: 20100289535
    Abstract: An integrated gate driver circuit includes an output drive circuit and a voltage stabilizing circuit. The voltage stabilizing circuit is configured to stabilize an output voltage outputted by the output drive circuit thereby reducing the ripple of the output voltage.
    Type: Application
    Filed: May 18, 2010
    Publication date: November 18, 2010
    Applicant: HANNSTAR DISPLAY CORP.
    Inventors: Yan Jou CHEN, Hsien Cheng CHANG
  • Publication number: 20100259530
    Abstract: A gate driving circuit receives a plurality of clock signals in a sequence and includes a plurality of cascaded drive units sequentially outputting an output signal, wherein a first-stage drive unit of the gate driving circuit receives a scan start signal or a scan end signal while a last-stage drive unit thereof receives a scan end signal or a scan start signal; wherein a driving direction of the gate driving circuit is reversed by reversing the sequence of the clock signals and exchanging the scan start signal and the scan end signal. The present invention further provides a driving method of a gate driving circuit.
    Type: Application
    Filed: April 1, 2010
    Publication date: October 14, 2010
    Applicant: HANNSTAR DISPLAY CORP.
    Inventors: Hsien Cheng CHANG, Yan Jou CHEN
  • Publication number: 20100073065
    Abstract: An integrated gate driver circuit receives a plurality of clocks and includes a plurality of driving units cascaded in series. Each driving unit is for driving a load and includes an input terminal, an output terminal, a first switch and a second switch. The first switch has a first terminal coupled to the input terminal, a second terminal coupled to a first node, and a control terminal receiving a first clock, and the first switch is turned on when the first clock is at high level. The second switch has a first terminal receiving a second clock, a second terminal coupled to the output terminal, and a control terminal coupled to the first node, wherein the second clock charges and discharges the load through the second switch when the first node is at high level; wherein the output terminal of each driving unit is coupled to the input terminal of the immediately succeeding driving unit.
    Type: Application
    Filed: September 16, 2009
    Publication date: March 25, 2010
    Applicant: HANNSTAR DISPLAY CORP.
    Inventors: Yan Jou CHEN, Yung Hsin LU, Chia Hua YU, Sung Chun LIN
  • Publication number: 20100013804
    Abstract: A gate line driving circuit comprises a driving chip comprising first and second output ports, a LCD panel comprising first, second and third gate lines, a first switch and a second switch. Two terminals of the first gate line are respectively connected to the first output port and the control terminal of the first switch. Two terminals of the third gate line are respectively connected to the second output port and the control terminal of the second switch. The input terminal of the first switch electrically connects an operating voltage and the output terminal of the first switch electrically connects to the input terminal of the second switch. The output terminal of the second switch electrically connects a ground point, and one terminal of the second gate line is connected to between the output terminal of the first switch and the input terminal of the second switch.
    Type: Application
    Filed: July 13, 2009
    Publication date: January 21, 2010
    Inventors: Yan-Jou CHEN, Hung-Jen Wang
  • Publication number: 20090154628
    Abstract: The invention provides scan signal generating circuits and scan signal generating methods thereof. The scan signal generating circuit comprises a first, a second and a third switch and a capacitor, and generates a scan signal driving a pixel. The first switch is turned on to couple an input signal to a first node when a first clock signal is high. The second switch, controlled according to the voltage level at the first node, is turned on to couple a second clock signal that has an inverse phase of the first clock signal to an output terminal of the scan signal generating circuit when the voltage level at the first node is high. When the first clock signal is high, the third switch is turned on to couple the output terminal to a first voltage source. The first node is coupled to ground by the capacitor.
    Type: Application
    Filed: January 28, 2008
    Publication date: June 18, 2009
    Applicant: HANNSTAR DISPLAY CORP.
    Inventors: Yan-Jou Chen, Yu-Chiung Yeh, Hung-Jen Wang, Yu-Ting Chen
  • Publication number: 20090109362
    Abstract: A display device is provided. The display device includes at least a substrate having a display region and a periphery region, a first ESD circuit and a pad disposed on the periphery region respectively. The pad has a first end near the display region and a second end near an edge of the substrate. A first connection line extended from the first end is electrically connected with a second connection line extended from the ESD circuit.
    Type: Application
    Filed: August 1, 2008
    Publication date: April 30, 2009
    Applicant: HANNSTAR DISPLAY CORPORATION
    Inventors: Yan-Jou Chen, Yu-Chiung Yeh, Yu-Ting Chen, Hung-Jen Wang