Abstract: A high electron mobility transistor (HEMT) and method for forming the same are disclosed. The high electron mobility transistor has a GaN epi-layer, a source ohmic contact, a drain ohmic contact, a gate structure, a first metal electrode contact and a first passivation layer. The source ohmic contact and the drain ohmic contact are disposed on the epi-layer. The gate structure is disposed on the epi-layer and between the source ohmic contact and the drain ohmic contact. The first metal electrode contact is disposed above the gate structure. The first passivation layer is sandwiched between the first metal electrode contact and the gate structure.

Abstract: This disclosure relates to a semiconductor device, and associated method of manufacture. The semiconductor device includes, a MOSFET integrated with a p-n junction, the p-n junction arranged as a clamping diode across a source contact and a drain contact of the MOSFET. The MOSFET defines a first breakdown voltage, and the clamping diode defines a second breakdown voltage, and the first breakdown voltage is greater than the second breakdown voltage. A series resistance of the clamping diode includes a drift resistance and a clamping resistance, and the drift resistance is formed together with the clamping diode and the clamping resistance is formed independently from the clamping diode and configured to secure a uniform avalanche current.

Abstract: A high electron mobility transistor (HEMT) includes a GaN epi-layer, a first passivation layer, a source electrode metal, a drain electrode metal, a gate electrode metal, and a field plate. The first passivation layer is deposited on the GaN epi-layer. The source electrode metal, the drain electrode metal, and the gate electrode are recessed into the first passivation layer and deposited on the GaN epi-layer. The source electrode metal has a source field plate with a source field plate length Lsf. The drain electrode metal has a drain field plate with a drain field plate length Ldf, wherein Ldf>Lsf. The gate electrode is situated between the source electrode metal and the drain electrode metal. The field plate is situated between the gate electrode and the drain electrode metal.

Abstract: A switch circuit, a mixer, and an electronic device, where the switch circuit includes a first metal oxide semiconductor (MOS) transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor, both a gate of the first MOS transistor and a gate of the fourth MOS transistor are connected to a first port, and both a gate of the second MOS transistor and a gate of the third MOS transistor are connected to a second port; and a lead between the gate of the first MOS transistor and the first port, a lead between the gate of the second MOS transistor and the second port, a lead between the gate of the third MOS transistor and the second port, and a lead between the gate of the fourth MOS transistor and the first port all have an equal length. In this way, linearity is relatively high.

Abstract: A high electron mobility transistor (HEMT) and method for forming the same are disclosed. The high electron mobility transistor has a GaN epi-layer, a source ohmic contact, a drain ohmic contact, a gate structure, a first metal electrode contact and a first passivation layer. The source ohmic contact and the drain ohmic contact are disposed on the epi-layer. The gate structure is disposed on the epi-layer and between the source ohmic contact and the drain ohmic contact. The first metal electrode contact is disposed above the gate structure. The first passivation layer is sandwiched between the first metal electrode contact and the gate structure.

Abstract: A high electron mobility transistor (HEMT) includes a GaN epi-layer, a first passivation layer, a source electrode metal, a drain electrode metal, a gate electrode metal, and a field plate. The first passivation layer is deposited on the GaN epi-layer. The source electrode metal, the drain electrode metal, and the gate electrode are recessed into the first passivation layer and deposited on the GaN epi-layer. The source electrode metal has a source field plate with a source field plate length Lsf. The drain electrode metal has a drain field plate with a drain field plate length Ldf, wherein Ldf>Lsf. The gate electrode is situated between the source electrode metal and the drain electrode metal. The field plate is situated between the gate electrode and the drain electrode metal.

Abstract: A high electron mobility transistor (HEMT) and method for forming the same are disclosed. The high electron mobility transistor has a GaN epi-layer, a source ohmic contact, a drain ohmic contact, a gate structure, a first metal electrode contact and a first passivation layer. The source ohmic contact and the drain ohmic contact are disposed on the epi-layer. The gate structure is disposed on the epi-layer and between the source ohmic contact and the drain ohmic contact. The first metal electrode contact is disposed above the gate structure. The first passivation layer is sandwiched between the first metal electrode contact and the gate structure.

Abstract: This disclosure relates to a semiconductor device, and associated method of manufacture. The semiconductor device includes, a MOSFET integrated with a p-n junction, the p-n junction arranged as a clamping diode across a source contact and a drain contact of the MOSFET. The MOSFET defines a first breakdown voltage, and the clamping diode defines a second breakdown voltage, and the first breakdown voltage is greater than the second breakdown voltage. A series resistance of the clamping diode includes a drift resistance and a clamping resistance, and the drift resistance is formed together with the clamping diode and the clamping resistance is formed independently from the clamping diode and configured to secure a uniform avalanche current.

Abstract: A switch circuit, a mixer, and an electronic device, where the switch circuit includes a first metal oxide semiconductor (MOS) transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor, both a gate of the first MOS transistor and a gate of the fourth MOS transistor are connected to a first port, and both a gate of the second MOS transistor and a gate of the third MOS transistor are connected to a second port; and a lead between the gate of the first MOS transistor and the first port, a lead between the gate of the second MOS transistor and the second port, a lead between the gate of the third MOS transistor and the second port, and a lead between the gate of the fourth MOS transistor and the first port all have an equal length. In this way, linearity is relatively high.

Abstract: The present disclosure relates to a semiconductor device, and associated method of manufacture. The semiconductor device includes, MOSFET integrated with a p-n junction, the p-n junction arranged as a clamping diode across a source contact and a drain contact of the MOSFET. The MOSFET defines a first breakdown voltage and the clamping diode defines a second breakdown voltage, with the first breakdown voltage being greater than the second breakdown voltage so that the clamp diode is configured and arranged to receive a low avalanche current and the MOSFET is configured and arranged to receive a high avalanche current.

Abstract: The present disclosure relates to a semiconductor device, and associated method of manufacture. The semiconductor device includes, MOSFET integrated with a p-n junction, the p-n junction arranged as a clamping diode across a source contact and a drain contact of the MOSFET. The MOSFET defines a first breakdown voltage and the clamping diode defines a second breakdown voltage, with the first breakdown voltage being greater than the second breakdown voltage so that the clamp diode is configured and arranged to receive a low avalanche current and the MOSFET is configured and arranged to receive a high avalanche current.

Abstract: Various aspects of the disclosure are directed to circuitry coupled for controlling current flow, such as in a cascode arrangement. As may be consistent with one or more embodiments, an apparatus includes a first transistor having a gate, source, channel and drain, and a second transistor having a gate, and having a stacked source, channel and drain. A conductive clip plate electrically connects the drain of the second transistor to the source of the first transistor, and another conductor electrically connects the source of the second transistor to the gate of the first transistor. The second transistor operates with the connecting structure to provide power by controlling the first transistor in an off-state and in an on-state.

Abstract: Various aspects of the disclosure are directed to circuitry coupled for controlling current flow, such as in a cascode arrangement. As may be consistent with one or more embodiments, an apparatus includes a first transistor having a gate, source, channel and drain, and a second transistor having a gate, and having a stacked source, channel and drain. A conductive clip plate electrically connects the drain of the second transistor to the source of the first transistor, and another conductor electrically connects the source of the second transistor to the gate of the first transistor. The second transistor operates with the connecting structure to provide power by controlling the first transistor in an off-state and in an on-state.

Abstract: Aspects of the present disclosure are directed to circuitry operable with enhanced capacitance and mitigation of avalanche breakdown. As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves respective transistors of a cascode circuit, one of which controls the other in an off state by applying a voltage to a gate thereof. A plurality of doped regions are separated by trenches, with the conductive trenches being configured and arranged with the doped regions to provide capacitance across the source and the drain of the second transistor, and restricting voltage at one of the source and the drain of the second transistor, therein mitigating avalanche breakdown of the second transistor.

Abstract: Aspects of the present disclosure are directed to circuitry operable with enhanced capacitance and mitigation of avalanche breakdown. As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves respective transistors of a cascode circuit, one of which controls the other in an off state by applying a voltage to a gate thereof. A plurality of doped regions are separated by trenches, with the conductive trenches being configured and arranged with the doped regions to provide capacitance across the source and the drain of the second transistor, and restricting voltage at one of the source and the drain of the second transistor, therein mitigating avalanche breakdown of the second transistor.