Abstract: A semiconductor package includes a substrate, a first insulation layer, a conductive pad, a second insulation layer and a conductive trace. The first insulation layer is formed on the substrate and having a first through hole. The conductive pad is formed on the substrate through the first through hole. The second insulation layer has a first surface and a second through hole, wherein the second through hole extends to the conductive pad from the first surface. The conductive trace has a second surface and is connected to the conductive pad through the second through hole. The entire of the first surface is in the same level, and the entire of the second surface is in the same level.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a gate strip, a source doped region and a body doped region. The substrate has an active region. The gate strip is disposed on the substrate within the active region. The gate strip extends along a first direction. The source doped region is located in the active region and adjacent to a first side of the gate strip along the first direction. The body doped region is located in the active region and adjacent to the first side of the gate strip. The body doped region and the source doped region have opposite conductivity types. The body doped region has a first length along a second direction that is different from the first direction, wherein the first length gradually changes along the first direction.

Abstract: A semiconductor device includes a semiconductor die having an active surface, an opposite surface, a vertical sidewall extending between the active surface and the opposite surface, and input/output (I/O) connections disposed on the active surface. A redistribution layer (RDL) is disposed on the active surface of the semiconductor die. A plurality of first connecting elements is disposed on the RDL. A molding compound encapsulates the opposite surface and the vertical sidewall of the semiconductor die. The molding compound also covers the RDL and surrounds the plurality of first connecting elements. An interconnect substrate is mounted on the plurality of first connecting elements and on the molding compound.

Abstract: A power supplying system for supplying power in an electronic device includes a plurality of rechargeable batteries coupled to a functional block of the electronic device. The rechargeable batteries at least include a first battery and a second batter. In a normal mode, the first battery and the second battery are connected in parallel between a system voltage supplying node and a ground node, and in a charging mode, the first battery and the second battery are connected in serial between a charge input node and the ground node.

Abstract: A semiconductor device includes a semiconductor component and a silicon-based passive component. The silicon-based passive component is stacked on the semiconductor component in a thickness direction of the semiconductor component.

Abstract: A power supplying system for supplying power in an electronic device includes rechargeable batteries coupled to a functional block of the electronic device. The rechargeable batteries include a first battery and a second battery. In a normal mode, the first battery and the second battery are connected in parallel between a system voltage supplying node and a ground node, in a first state of a charging mode, the first battery and the second battery are connected in serial between a charge input node and the ground node with a first terminal of the second battery being connected to the system voltage supplying node, and in a second state of the charging mode, the first battery and the second battery are connected in serial between the charge input node and the ground node with a first terminal of the first battery being connected to the system voltage supplying node.

Abstract: A MOS transistor structure is provided. The MOS transistor structure includes a semiconductor substrate having an active area including a first edge and a second edge opposite thereto. A gate layer is disposed on the active area of the semiconductor substrate and has a first edge extending across the first and second edges of the active area. A source region having a first conductivity type is in the active area at a side of the first edge of the gate layer and between the first and second edges of the active area. First and second heavily doped regions of a second conductivity type are in the active area adjacent to the first and second edges thereof, respectively, and spaced apart from each other by the source region.

Abstract: A semiconductor device includes a semiconductor substrate having a well region and a gate structure formed over the well region of the semiconductor substrate. The semiconductor device also includes a gate spacer structure having a first spacer portion and a second spacer portion on opposite sidewalls of the gate structure. The semiconductor device also includes a source region and a drain region formed in the semiconductor substrate. The source region and a drain region are separated from the gate structure. The source region is adjacent to the first spacer portion of the gate spacer structure, and the drain region is adjacent to the second spacer portion of the gate spacer structure. The bottom width of the second spacer portion is greater than the bottom width of the first spacer portion.

Abstract: A semiconductor package includes a substrate, a first insulation layer, a conductive via and a conductive trace. The substrate includes a conductive component. The first insulation layer is formed on the substrate and having a first through hole exposing the conductive component. The conductive via is formed within the first through hole. The conductive trace is directly connected to the conductive via which is located directly above the first through hole.

Abstract: A semiconductor package includes a substrate, a first insulation layer, a conductive pad, a second insulation layer and a conductive trace. The first insulation layer is formed on the substrate and having a first through hole. The conductive pad is formed on the substrate through the first through hole. The second insulation layer has a first surface and a second through hole, wherein the second through hole extends to the conductive pad from the first surface. The conductive trace has a second surface and is connected to the conductive pad through the second through hole. The entire of the first surface is in the same level, and the entire of the second surface is in the same level.

Abstract: A semiconductor device includes a semiconductor substrate having a well region and a gate structure formed over the well region of the semiconductor substrate. The gate structure has a first sidewall and a second sidewall. The second sidewall is opposite the first sidewall. The semiconductor device also includes a gate spacer structure having two asymmetrical portions. One of the asymmetrical portions is formed on the first sidewall of the gate structure, and the other asymmetrical portion is formed on the second sidewall of the gate structure. The semiconductor device includes a source region and a drain region formed in the semiconductor substrate and aligned with the outer edges of the asymmetrical portions of the gate spacer structure. In some embodiments, the lateral distance between the drain region and the gate structure is greater than the lateral distance between the source region and the gate structure.

Abstract: A semiconductor device includes a semiconductor die having an active surface, an opposite surface, a vertical sidewall extending between the active surface and the opposite surface, and input/output (I/O) connections disposed on the active surface. A redistribution layer (RDL) is disposed on the active surface of the semiconductor die. A plurality of first connecting elements is disposed on the RDL. A molding compound encapsulates the opposite surface and the vertical sidewall of the semiconductor die. The molding compound also covers the RDL and surrounds the plurality of first connecting elements. An interconnect substrate is mounted on the plurality of first connecting elements and on the molding compound.

Abstract: A wafer-level chip-size package includes a semiconductor structure. A bonding pad is formed over the semiconductor structure, including a plurality of conductive segments. A conductive component is formed over the semiconductor structure, being adjacent to the bonding pad. A passivation layer is formed, exposing a portions of the conductive segments of the first bonding pad. A conductive redistribution layer is formed over the portions of the conductive segments of the first bonding pad exposed by the passivation layer. A planarization layer is formed over the passivation layer and the conductive redistribution layer, exposing a portion of the conductive redistribution layer. A UBM layer is formed over the planarization layer and the portion of the conductive redistribution layer exposed by the planarization layer. A conductive bump is formed over the UBM layer.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, a first well region formed in a portion of the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type. A second well region is formed in a portion of the first well region, having the first conductivity type. A first gate structure is formed over a portion of the second well region and a portion of the first well region. A first doped region is formed in a portion of the second well region. A second doped region is formed in a portion of the first well region, having the second conductivity type. A second dielectric layer is formed over a portion of the first gate structure, a portion of the first well region, and a portion of the second doped region.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, a first well region formed in a portion of the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type. A second well region is formed in a portion of the first well region, having the first conductivity type. A first gate structure is formed over a portion of the second well region and a portion of the first well region. A first doped region is formed in a portion of the second well region. A second doped region is formed in a portion of the first well region, having the second conductivity type. A second dielectric layer is formed over a portion of the first gate structure, a portion of the first well region, and a portion of the second doped region.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, a first well region formed in a portion of the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type. A second well region is formed in a portion of the first well region, having the first conductivity type. A first gate structure is formed over a portion of the second well region and a portion of the first well region. A first doped region is formed in a portion of the second well region. A second doped region is formed in a portion of the first well region, having the second conductivity type. A second dielectric layer is formed over a portion of the first gate structure, a portion of the first well region, and a portion of the second doped region.

Abstract: A semiconductor device capable of high-voltage operation includes a semiconductor substrate having a first conductivity type. A first well doped region is formed in a portion of the semiconductor substrate. The first well doped region has a second conductivity type. A first doped region is formed on the first well doped region, having the second conductivity type. A second doped region is formed on the first well doped region and is separated from the first doped region, having the second conductivity type. A first gate structure is formed over the first well doped region and is adjacent to the first doped region. A second gate structure is formed beside the first gate structure and is close to the second doped region. A third gate structure is formed overlapping a portion of the first gate structure and a first portion of the second gate structure.

Abstract: A semiconductor device includes a semiconductor substrate and a passive component. The passive component is formed on the semiconductor substrate and includes a first polysilicon (poly) layer, a salicide blockage (SAB) layer and a first salicide layer. The SAB layer is formed on the first poly layer. The first salicide layer is formed on the SAB layer.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, a first well region formed in a portion of the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type. A second well region is formed in a portion of the first well region, having the first conductivity type. A first gate structure is formed over a portion of the second well region and a portion of the first well region. A first doped region is formed in a portion of the second well region. A second doped region is formed in a portion of the first well region, having the second conductivity type. A second dielectric layer is formed over a portion of the first gate structure, a portion of the first well region, and a portion of the second doped region.

Abstract: A semiconductor device capable of high-voltage operation includes a semiconductor substrate, a first well region, a second well region, a first gate structure, a first doped region, a second doped region, and a second gate structure. The first well region is formed in a portion of the semiconductor substrate. The second well region is formed in a portion of the first well region. The first gate structure is formed over a portion of the second well region and a portion of the first well region. The first doped region is formed in a portion of the second well region. The second doped region is formed in a portion of the first well region. The second gate structure is formed over a portion of the first gate structure, a portion of the first well region, and a portion of the second doped region.