Patents by Inventor Yan-Man Tsui

Yan-Man Tsui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7094640
    Abstract: A method of forming a trench MOSFET device includes depositing an epitaxial layer over a substrate, both having the first conductivity type, the epitaxial layer having a lower majority carrier concentration than the substrate, forming a body region of a second conductivity type within an upper portion of the epitaxial layer, etching a trench extending into the epitaxial layer from an upper surface of the epitaxial layer, the trench extending to a greater depth from the upper surface of the epitaxial layer than the body region, forming a doped region of the first conductivity type between a bottom portion of the trench and substrate, the doped region having a majority carrier concentration that is lower than that of the substrate and higher than that of the epitaxial layer, wherein the doped region is diffused and spans 100% of the distance from the trench bottom portion to the substrate, forming an insulating layer lining at least a portion of the trench, forming a conductive region within the trench adjacent
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: August 22, 2006
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So, John E. Amato, Yan Man Tsui
  • Patent number: 7015125
    Abstract: A trench MOSFET transistor device and a method of making the same.
    Type: Grant
    Filed: November 8, 2004
    Date of Patent: March 21, 2006
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So, John E. Amato, Yan Man Tsui
  • Patent number: 6927094
    Abstract: The present invention provides a semiconductor device packaging assembly and method for manufacturing the assembly. Preferably, the method of the present invention is used to assemble a plurality of semiconductor chips, such that the throughput of assembly can be enhanced. The method comprises the steps of: providing a bottom frame matrix including a plurality of bottom frame units, each of which unit comprises a bottom supporting portion and a bottom frame portion; providing a bridge frame including a plurality of bridge frame units, each of which unit comprises a bridge frame portion and a plurality of conducting bars; placing each of the semiconductor chips on each of the bottom supporting portions, respectively; and bonding each bottom frame unit and each bridge frame unit together, wherein, the conducting bars extending from each bridge frame portion toward corresponding chips are electrically coupled to bonding areas of the corresponding chips.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: August 9, 2005
    Assignee: General Semiconductor of Taiwan, Ltd.
    Inventors: Max Chen, Ching Lu Hsu, Kuang Hann Lin, Yan-Man Tsui
  • Patent number: 6822288
    Abstract: A trench MOSFET transistor device and a method of making the same.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: November 23, 2004
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So, John E. Amato, Yan Man Tsui
  • Patent number: 6781196
    Abstract: A trench DMOS transistor cell is provided that includes a substrate of a first conductivity type and a body region located on the substrate, which has a second conductivity type. At least one trench extends through the body region and the substrate. An insulating layer lines the trench and a conductive electrode is placed in the trench overlying the insulating layer. A source region of the first conductivity type is located in the body region adjacent to the trench. The trench has sidewalls that define a polygon in the plane of the substrate so that adjacent sidewalls contact one another at an angle greater than 90 degrees.
    Type: Grant
    Filed: March 11, 2002
    Date of Patent: August 24, 2004
    Assignee: General Semiconductor, Inc.
    Inventors: Koon Chong So, Fwu-Iuan Hshieh, Yan Man Tsui
  • Patent number: 6762098
    Abstract: An integrated circuit having a plurality of trench Schottky barrier rectifiers within one or more rectifier regions and a plurality of trench DMOS transistors within one or more transistor regions.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: July 13, 2004
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Yan Man Tsui, Koon Chong So
  • Publication number: 20040113203
    Abstract: A trench MOSFET device and method of making the same.
    Type: Application
    Filed: December 1, 2003
    Publication date: June 17, 2004
    Inventors: Fwu-Iuan Hshieh, Koon Chong So, John E. Amato, Yan Man Tsui
  • Patent number: 6740951
    Abstract: A Schottky rectifier includes a semiconductor structure having first and second opposing faces each extending to define an active semiconductor region and a termination semiconductor region. The semiconductor structure includes a cathode region of the first conductivity type adjacent the first face and a drift region of the first conductivity type adjacent the second face. The drift region has a lower net doping concentration than that of the cathode region. A plurality of trenches extends from the second face into the semiconductor structure and defines a plurality of mesas within the semiconductor structure. At least one of the trenches is located in each of the active and the termination semiconductor regions. A first insulating region is located adjacent the semiconductor structure in the plurality of trenches. A second insulating region electrically isolates the active semiconductor region from the termination semiconductor region.
    Type: Grant
    Filed: May 22, 2001
    Date of Patent: May 25, 2004
    Assignee: General Semiconductor, Inc.
    Inventors: Yan Man Tsui, Fwu-Iuan Hshieh, Koon Chong So
  • Patent number: 6713352
    Abstract: A trench MOSFET includes a plurality of trench segments in an upper surface of an epitaxial layer, extending through a second conductivity type region into a first conductivity type epitaxial region, segment at least partially separated from an adjacent segment by a terminating region, and the trench segments defining a plurality of polygonal body regions within the second conductivity type. A first insulating layer at least partially lines each trench and a plurality of first conductive regions are provided within the trench segments adjacent to the first layer. Each of the conductive regions is connected to an adjacent first conductive region by a connecting conductive region, overlying the terminating region, that bridges at least one of the terminating regions and a plurality of first conductivity type source regions are within upper portions of the polygonal body regions and adjacent the trench segments, the source regions positioned outside the terminating regions.
    Type: Grant
    Filed: September 13, 2002
    Date of Patent: March 30, 2004
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So, Yan Man Tsui
  • Patent number: 6707127
    Abstract: A Schottky rectifier is provided. The Schottky rectifier comprises: (a) a semiconductor region having first and second opposing faces, with the semiconductor region comprising a cathode region of first conductivity type adjacent the first face and a drift region of the first conductivity type adjacent the second face, and with the drift region having a lower net doping concentration than that of the cathode region; (b) one or more trenches extending from the second face into the semiconductor region and defining one or more mesas within the semiconductor region; (c) an insulating region adjacent the semiconductor region in lower portions of the trench; (d) and an anode electrode that is (i) adjacent to and forms a Schottky rectifying contact with the semiconductor at the second face, (ii) adjacent to and forms a Schottky rectifying contact with the semiconductor region within upper portions of the trench and (iii) adjacent to the insulating region within the lower portions of the trench.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: March 16, 2004
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Max Chen, Koon Chong So, Yan Man Tsui
  • Patent number: 6657254
    Abstract: A trench MOSFET device and method of making the same.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: December 2, 2003
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So, John E. Amato, Yan Man Tsui
  • Publication number: 20030207538
    Abstract: An integrated circuit having a plurality of trench Schottky barrier rectifiers within one or more rectifier regions and a plurality of trench DMOS transistors within one or more transistor regions.
    Type: Application
    Filed: May 30, 2003
    Publication date: November 6, 2003
    Inventors: Fwu-Iuan Hshieh, Yan Man Tsui, Koon Chong So
  • Publication number: 20030205792
    Abstract: The present invention provides a semiconductor device packaging assembly and method for manufacturing the assembly. Preferably, the method of the present invention is used to assemble a plurality of semiconductor chips, such that the throughput of assembly can be enhanced. The method comprises the steps of: providing a bottom frame matrix including a plurality of bottom frame units, each of which unit comprises a bottom supporting portion and a bottom frame portion; providing a bridge frame including a plurality of bridge frame units, each of which unit comprises a bridge frame portion and a plurality of conducting bars; placing each of the semiconductor chips on each of the bottom supporting portions, respectively, and bonding each bottom frame unit and each bridge frame unit together, wherein, the conducting bars extending from each bridge frame portion toward corresponding chips are electrically coupled to bonding areas of the corresponding chips.
    Type: Application
    Filed: May 30, 2003
    Publication date: November 6, 2003
    Inventors: Max Chen, C. L. Hsu, K. H. Lin, Yan-Man Tsui
  • Patent number: 6620691
    Abstract: A method for making trench DMOS is provided that improves the breakdown voltage of the oxide layer in a device having at least a first trench disposed in the active region of the device and a second trench disposed in the termination region of the device. In accordance with the method, mask techniques are used to thicken the oxide layer in the vicinity of the top corner of the second trench, thereby compensating for the thinning of this region (and the accompanying reduction in breakdown voltage) that occurs due to the two-dimensional oxidation during the manufacturing process.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: September 16, 2003
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So, Yan Man Tsui
  • Publication number: 20030168696
    Abstract: A trench DMOS transistor cell is provided that includes a substrate of a first conductivity type and a body region located on the substrate, which has a second conductivity type. At least one trench extends through the body region and the substrate. An insulating layer lines the trench and a conductive electrode is placed in the trench overlying the insulating layer. A source region of the first conductivity type is located in the body region adjacent to the trench. The trench has sidewalls that define a polygon in the plane of the substrate so that adjacent sidewalls contact one another at an angle greater than 90 degrees.
    Type: Application
    Filed: March 11, 2002
    Publication date: September 11, 2003
    Inventors: Koon Chong So, Fwu-Iuan Hshieh, Yan Man Tsui
  • Patent number: 6593620
    Abstract: An integrated circuit having a plurality of trench Schottky barrier rectifiers within one or more rectifier regions and a plurality of trench DMOS transistors within one or more transistor regions.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: July 15, 2003
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Yan Man Tsui, Koon Chong So
  • Publication number: 20030107080
    Abstract: A trench MOSFET transistor device and a method of making the same.
    Type: Application
    Filed: November 20, 2001
    Publication date: June 12, 2003
    Inventors: Fwu-Iuan Hshieh, Koon Chong So, John E. Amato, Yan Man Tsui
  • Patent number: 6576952
    Abstract: In a first aspect of the invention, a modified semiconductor substrate is provided. The modified substrate comprises: (1) a semiconductor substrate; (2) at least one buffer layer provided over at least a portion of the substrate; and (3) a plurality of trenches comprising (a) a plurality of internal trenches that extend into the semiconductor substrate and (b) at least one shallow peripheral trench that extends into the at least one buffer layer but does not extend into the semiconductor substrate. In another aspect, a method of selectively providing trenches in a semiconductor substrate is provided. According to a further aspect of the invention, a trench DMOS transistor structure that includes at least one peripheral trench and a plurality of internal trenches is provided.
    Type: Grant
    Filed: January 17, 2002
    Date of Patent: June 10, 2003
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So, Yan Man Tsui
  • Patent number: 6576985
    Abstract: The present invention provides a semiconductor device packaging assembly and method for manufacturing the assembly. Preferably, the method of the present invention is used to assemble a plurality of semiconductor chips, such that the throughput of assembly can be enhanced, by providing a bottom frame matrix including a plurality of bottom frame units, each of which unit includes a bottom supporting portion and a bottom frame portion; providing a bridge frame including a plurality of bridge frame units, each of which unit includes a bridge frame portion and a plurality of conducting bars; placing each of the semiconductor chips on each of the bottom supporting portions, respectively; and bonding each bottom frame unit and each bridge frame unit together, wherein, the conducting bars extending from each bridge frame portion toward corresponding chips are electrically coupled to bonding areas of the corresponding chips.
    Type: Grant
    Filed: January 18, 2001
    Date of Patent: June 10, 2003
    Assignee: General Semiconductor Taiwan, Ltd.
    Inventors: Max Chen, Ching Lu Hsu, Kuang Hann Lin, Yan-Man Tsui
  • Publication number: 20030094624
    Abstract: A trench MOSFET device and method of making the same.
    Type: Application
    Filed: November 21, 2001
    Publication date: May 22, 2003
    Inventors: Fwu-Iuan Hshieh, Koon Chong So, John E. Amato, Yan Man Tsui