Abstract: Provided herein is a compound of Formula (IB), a stereoisomer thereof, a pharmaceutically acceptable salt thereof, a pharmaceutically acceptable salt of the stereoisomer thereof, a prodrug thereof, a deuterated molecule thereof or a conjugated form thereof; composition containing the same and the use thereof.

Abstract: A method and system for detecting road intelligent compaction index, so as to solve the problem of inaccurate use of a road intelligent compaction index due to the fact that existing harmonic ratio indexes do not consider the influence of a non-integral period on the accuracy and also do not consider a higher harmonic. According to the disclosure, a relative relationship between amplitudes of the higher harmonic and a fundamental wave in an acceleration time domain signal is considered based on the related art, the amplitude of the higher harmonic is introduced into a main body road intelligent compaction index of an road intelligent compaction index, and a precondition for the use of the road intelligent compaction index of the main body is established, that is, a machine-material decoupling control the machine-material decoupling control index.

Abstract: A method for driving a display panel, a display drive device, and a display device. The method includes, during a data refresh stage of at least one display frame, loading a gate turn-on voltage to a gate line, and loading, on each data line, a data voltage of an image to be displayed, so that each sub-pixel inputs a corresponding data voltage, and during a blanking time period, loading a gate turn-off voltage to a gate line, and loading a compensation voltage to each data line. When a data voltage in a sub-pixel connected to a data line is greater than a common electrode voltage, a compensation voltage is less than the data voltage in the sub-pixel connected to the data line, and/or when the data voltage in the sub-pixel is less than the common electrode voltage, the compensation voltage is greater than the data voltage in the sub-pixel.

Abstract: Provided are a compound of formula (I) that inhibit the activity of PARP7, a stereoisomer thereof, a deuterated derivative thereof, or a pharmaceutically acceptable salt thereof, an intermediate to prepare the compound, a process to prepare the compound, a composition comprising the same, and the methods of using the same.

Abstract: The disclosure discloses a method and system for detecting road intelligent compaction index, so as to solve the problem of inaccurate use of a road intelligent compaction index due to the fact that existing harmonic ratio indexes do not consider the influence of a non-integral period on the accuracy and also do not consider a higher harmonic. According to the disclosure, a relative relationship between amplitudes of the higher harmonic and a fundamental wave in an acceleration time domain signal is considered based on the related art, the amplitude of the higher harmonic is introduced into a main body road intelligent compaction index of an road intelligent compaction index, and a precondition for the use of the road intelligent compaction index of the main body is established, that is, a machine-material decoupling control the machine-material decoupling control index.

Abstract: A display apparatus includes sub-pixels, at least one gate line group and a scan drive circuit. The gate line group includes a first gate line, a second gate line and a third gate line. The scan drive circuit outputs, in a frame scan cycle, a first scan signal to the first gate line, a second scan signal to the second gate line, and a third scan signal to the third gate line in sequence. Durations of effective scan periods of the scan signals are equal. A start moment of the effective scan period of the second scan signal is delayed by a first time length compared with that of the first scan signal. A start moment of the effective scan period of the third scan signal is delayed by a second time length less than the first time length compared with that of the second scan signal.

Abstract: A driving circuit, a display device, and a driving method are disclosed. The driving circuit includes a level conversion unit and a gate electrode driving unit; and the gate electrode driving unit is configured to sequentially shift and output a plurality of first gate scan signals by a first portion of the 2n gate signal output terminals in response to a first portion of the plurality of first output signals received at a first moment by a first portion of the plurality of second clock signal input terminals, and sequentially output a plurality of second gate scan signals by a second portion of the 2n gate signal output terminals in response to a second portion of the plurality of first output signals received at a second moment by a second portion of the plurality of second clock signal input terminals.

Abstract: A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.

Abstract: A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.

Abstract: A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.

Abstract: An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess.

Abstract: A GaN transistor with reduced output capacitance and a method form manufacturing the same. The GaN transistor device includes a substrate layer, one or more buffer layer disposed on a substrate layer, a barrier layer disposed on the buffer layers, and a two dimensional electron gas (2DEG) formed at an interface between the barrier layer and the buffer layer. Furthermore, a gate electrode is disposed on the barrier layer and a dielectric layer is disposed on the gate electrode and the barrier layer. The GaN transistor includes one or more isolation regions formed in a portion of the interface between the at least one buffer layer and the barrier layer to remove the 2DEG in order to reduce output capacitance Coss of the GaN transistor.

Abstract: An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess.

Abstract: A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.

Abstract: A method for forming an enhancement mode GaN HFET device with an isolation area that is self-aligned to a contact opening or metal mask window. Advantageously, the method does not require a dedicated isolation mask and the associated process steps, thus reducing manufacturing costs. The method includes providing an EPI structure including a substrate, a buffer layer a GaN layer and a barrier layer. A dielectric layer is formed over the barrier layer and openings are formed in the dielectric layer for device contact openings and an isolation contact opening. A metal layer is then formed over the dielectric layer and a photoresist film is deposited above each of the device contact openings. The metal layer is then etched to form a metal mask window above the isolation contact opening and the barrier and GaN layer are etched at the portion that is exposed by the isolation contact opening in the dielectric layer.

Abstract: An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess.

Abstract: A GaN transistor with polysilicon layers for creating additional components for an integrated circuit. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.

Abstract: An integrated semiconductor device which includes a substrate layer, a buffer layer formed on the substrate layer, a gallium nitride layer formed on the buffer layer, and a barrier layer formed on the gallium nitride layer. Ohmic contacts for a plurality of transistor devices are formed on the barrier layer. Specifically, a plurality of first ohmic contacts for the first transistor device are formed on a first portion of the surface of the barrier layer, and a plurality of second ohmic contacts for the second transistor device are formed on a second portion of the surface of the barrier layer. In addition, one or more gate structures formed on a third portion of the surface of the barrier between the first and second transistor devices. Preferably, the one or more gate structures and the spaces between the gate structures and the source contacts of the transistor devices collectively form an isolation region that electrically isolates the first transistor device from the second transistor device.

Abstract: An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess.