Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

Abstract: A method of forming RMG multi-WF layers for an nFET and pFET, and the resulting device are provided. Embodiments include forming a Si fin; forming a nFET RMG trench and a pFET RMG trench; forming a first Ti layer in the nFET and pFET RMG trenches; implanting N2 in the first Ti layer vertically at a 0° implant angle in the pFET RMG trench; annealing the N2 implanted first Ti layer to form a TiN layer in the pFET RMG trench; stripping un-reacted Ti of the first Ti layer; forming a second Ti layer in the nFET and pFET RMG trenches; implanting Al or C in the second Ti layer vertically at 0°; annealing the Al or C implanted second Ti layer to form TiAl or TiC at a bottom of the nFET and pFET RMG trenches, respectively; and filling the nFET and pFET RMG trenches with Al or W.

Abstract: A method of forming RMG multi-WF layers for an nFET and pFET, and the resulting device are provided. Embodiments include forming a Si fin; forming a nFET RMG trench and a pFET RMG trench; forming a first Ti layer in the nFET and pFET RMG trenches; implanting N2 in the first Ti layer vertically at a 0° implant angle in the pFET RMG trench; annealing the N2 implanted first Ti layer to form a TiN layer in the pFET RMG trench; stripping un-reacted Ti of the first Ti layer; forming a second Ti layer in the nFET and pFET RMG trenches; implanting Al or C in the second Ti layer vertically at 0°; annealing the Al or C implanted second Ti layer to form TiAl or TiC at a bottom of the nFET and pFET RMG trenches, respectively; and filling the nFET and pFET RMG trenches with Al or W.

Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

Abstract: Methods of fabricating transistors having raised active region(s) with at least partially angled upper surfaces are provided. The method includes, for instance: providing a gate structure disposed over a substrate, the gate structure including a conformal spacer layer; forming a raised active region adjoining a sidewall of the conformal spacer layer; providing a protective material over the raised active region; selectively etching-back the sidewall of the conformal spacer layer, exposing a side portion of the raised active region below the protective material; and etching the exposed side portion of the raised active region to partially undercut the protective material, wherein the etching facilitates defining, at least in part, an at least partially angled upper surface of the raised active region of the transistor.

Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

Abstract: A semiconductor structure with wide-bottom and/or wide-top gates includes a semiconductor substrate, a source region(s), a drain region(s) associated with the source region(s), and a gate(s) associated with the source region(s) and the drain region(s) having a top portion and a bottom portion. One of the top portion and the bottom portion of the gate(s) is wider than the other of the top portion and bottom portion. The wide-bottom gate is created using a dummy wide-bottom gate etched from a layer of dummy gate material, creating spacers for the dummy gate, removing the dummy gate material and filling the opening created with conductive material. For the wide-top gate, first and second spacers are included, and instead of removing all the dummy gate material, only a portion is removed, exposing the first spacers. The exposed portion of the first spacers may either be completely or partially removed (e.g., tapered), in order to increase the area of the top portion of the gate to be filled.

Abstract: A method includes forming a gate structure by growing an interfacial layer on a substrate, depositing a High K layer on the interfacial layer, depositing a TiN Cap on the High K layer and forming a thin barrier layer on the TiN Cap. The gate structure is annealed.

Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

Abstract: A method includes forming a gate structure by growing an interfacial layer on a substrate, depositing a High K layer on the interfacial layer, depositing a TiN Cap on the High K layer and forming a thin barrier layer on the TiN Cap. The gate structure is annealed.

Abstract: A method of filling gaps between gates with doped flowable pre-metal dielectric (PMD) and the resulting device are disclosed. Embodiments include forming at least two dummy gates on a substrate, each dummy gate being surrounded by spacers; filling a gap between adjacent spacers of the at least two dummy gates with a flowable PMD; implanting a dopant in the flowable PMD; and annealing the flowable PMD. Doping the flowable PMD prevents erosion of the PMD, thereby providing a voidless gap-fill.

Abstract: A rack and an optical drive utilizing the same. The rack comprises at least one full tooth, a first tooth lower than the full tooth, and a second tooth with the same height as the full tooth. The second tooth is adjacent to the first tooth and comprises a chamfer which is on the tooth crest and faces the first tooth to prevent the rack from blocking the gear.