Abstract: A manufacturing method of a semiconductor device includes forming an epitaxial layer over a substrate, forming a well region and a source region in the epitaxial layer, forming a first trench in the epitaxial layer, in which the first trench has a round corner protruding to the well region, forming a second trench in the epitaxial layer, in which the bottom of the second trench is higher than the bottom of the first trench and the width of the second trench is greater than the width of the first trench, and forming a gate structure in the first trench and the second trench.

Abstract: A method includes forming a trench in a substrate, the trench extending downwards from a top surface of the substrate, in which the trench has a sidewall and a bottom surface, and an angle between the sidewall and the bottom surface is greater than or equal to 90 degrees, forming a well region at the top surface of the substrate, the sidewall and the bottom surface of the trench, forming a source region and a body contact region at the bottom surface of the trench, and the body contact region being adjacent to the source region, forming a gate structure along the top surface of the substrate, the sidewall and the bottom surface of the trench, and forming a source contact in the trench to penetrate the gate structure and electrically connect to the source region and the body contact region.

Abstract: A semiconductor structure includes a substrate, a gate structure, a first oxide layer, and a second oxide layer. The substrate has a trench. An inclined surface and a bottom surface of the trench have an obtuse angle therebetween. The gate structure is located in the trench. A width of a bottom surface of the gate structure is less than a width of a top surface of the gate structure. A cross-sectional profile of the gate structure is inverted trapezoid. The first oxide layer is located between the gate structure and the substrate. The second oxide layer is located on the top surface of the gate structure.

Abstract: A manufacturing method of a semiconductor device includes providing a substrate, forming a first trench in the substrate, in which a top of the first trench is greater than a bottom of the first trench, forming a well region and a source region at a side of the first trench, in which the source region is on the well region, forming a hard mask stack lining a surface of the substrate, forming a second trench in the hard mask stack, in which the bottom of the second trench is over the corner of the first trench, performing an implantation process to form a shielding doped region at a region of the substrate nearing the corner of the first trench, removing the hard mask stack, forming a gate dielectric layer lining the surface of the substrate, and forming a gate in the first trench.

Abstract: A circuit board module includes a circuit board and a plurality of capacitors. The circuit board has a plurality of standing feet for erecting on a main board, and the capacitors are symmetrically fixed on a first surface and a second surface opposite to the first surface of the circuit board. An opening is formed on the circuit board of the circuit board module and the opening is located between the capacitors. In addition, an electronic device adopting the circuit board module design is also disclosed herein.

Abstract: A simulated configuration evaluation apparatus is provided. The apparatus generates a virtual three-dimensional object placed in a first simulated pose based on a virtual three-dimensional object model in a virtual space, the virtual three-dimensional object includes transmitters, the transmitters are set on the virtual three-dimensional object in a first configuration, and the transmitters are configured to transmit a plurality of first signals. The apparatus receives second signals from the transmitters based on a viewpoint in the virtual space. The apparatus calculates a first estimated pose of the virtual three-dimensional object in the virtual space based on the second signals. The apparatus compares the first estimated pose and the first simulated pose to generate a first evaluating score corresponding to the first configuration.

Abstract: A virtual reality tracker includes a first part and a second part. The first part includes a plurality of first light-emitting diodes (LEDs) and an inner measurement unit (IMU). The inertial measurement unit is used for measuring the acceleration and the triaxial angular velocity of the first part. The second part includes a plurality of second light-emitting diodes. Moreover, the first part and the second part are connected by a flexible component.

Abstract: A memory chip includes a memory cell circuit, a periphery circuit, an interconnect structure, and a control logic circuit. The periphery circuit is positioned under the memory cell circuit and electrically connected to the memory cell circuit. The interconnect structure is positioned on a side surface of the memory cell circuit. The control logic circuit is positioned under the interconnect structure. The control logic circuit is electrically connected to the interconnect structure and the periphery circuit and includes a dynamic random-access memory.

Abstract: The present disclosure provides a semiconductor device including a drift layer above the substrate, a source/drain region above the drift layer, an oxide thin film on the source/drain region, a contact on the oxide thin film, and a gate structure adjacent to source/drain region. The oxide thin film directly contacts the top surface of the source/drain region and the bottom surface of the contact. The source/drain region includes a first doping region having a first conductive type and a second doping region having a second conductive type different from the first conductive type, in which the first doping region and the second doping region forms the top surface of the source/drain region. The conduction band energy level of the oxide thin film is lower than the conduction band energy level of the first doping region.

Abstract: Some embodiments of the present disclosure provide a method of forming a semiconductor device including forming a dielectric layer stack on an epitaxial layer. The dielectric layer stack includes at least one first layer and at least one second layer, the at least one first layer is made of a first material, the at least second layer is made of a second material different from the first material. The dielectric layer stack is patterned to form a staircase-shaped dielectric layer stack. An ion implantation process is performed to the epitaxial layer by using the staircase-shaped dielectric layer stack.

Abstract: A semiconductor structure includes a semiconductor epitaxial layer, a first semiconductor well, a second semiconductor well, a source doped region, a gate structure and a drain structure. The semiconductor epitaxial layer includes a first side and a second side opposite to the first side. The first semiconductor well is located on the first side of the semiconductor epitaxial layer. The second semiconductor well is located on the second side of the semiconductor epitaxial layer. The source doped region is located in the first semiconductor well. The gate structure overlaps the first semiconductor well and the source doped region on the first side of the semiconductor epitaxial layer. The drain structure includes a semiconductor substrate. The second side of the semiconductor epitaxial layer outside the second semiconductor well includes a connecting surface. The connecting surface of the semiconductor epitaxial layer is connected to the semiconductor substrate.

Abstract: A method of forming a semiconductor structure includes the following operations. A semiconductor epitaxial layer is formed on a first semiconductor substrate. A first side of the semiconductor epitaxial layer is adhered to a transfer substrate by an adhesive layer covering the first side of the semiconductor epitaxial layer. The semiconductor epitaxial layer and the first semiconductor substrate are turned over by the transfer substrate. The first semiconductor substrate is removed to expose a second side of the semiconductor epitaxial layer opposite to the first side. A first semiconductor doped region is formed on the second side of the semiconductor epitaxial layer. After the first semiconductor doped region is formed, the adhesive layer and the transfer substrate are removed.

Abstract: A semiconductor device includes a substrate, an epitaxial layer on the substrate, a first well region in the epitaxial layer, a source region in the first well region, a source contact, a base region wrapping around a sidewall of the source contact and a second well region wrapping around the base region. The substrate, the epitaxial layer and the source region include a plurality of dopants of a first semiconductor type. A bottom of the source contact is lower than a bottom of the first well region. The base region and the second well region include a plurality of dopants of a second semiconductor type. The second semiconductor type is different from the first semiconductor type, and a doping concentration of the base region is higher than a doping concentration of the first well region and a doping concentration of the second well region.

Abstract: The present disclosure provides a transistor structure including a semiconductor stack, a gate structure, and a conductive element. The semiconductor stack includes a drift layer above a substrate, a first doping region in the drift layer, and a depletion region in the drift layer adjacent to the first doping region. The drift region has a first conductive type, and the first doping region has a second conductive type. The gate structure is positioned on the semiconductor stack and covers the depletion region. The conductive element including a metal layer is in the depletion region, in which a top surface of the metal layer directly contacts a bottom surface of the gate structure.

Abstract: A semiconductor device includes a substrate, an epitaxial layer, a well region, a current spreading layer, a source region, a base region and a gate layer. The epitaxial layer is on the substrate. The well region is in the epitaxial layer. The current spreading layer is in the epitaxial layer and below the well region. The current spreading layer includes a plurality of the first doped regions and a plurality of the second doped regions, the first doped regions includes a plurality of dopants of the first semiconductor-type, the second doped regions includes a plurality of dopants of the second semiconductor-type, and the second semiconductor-type is different from the first semiconductor-type. The source region is in the well region. The base region is in the well region and adjacent to the source region. The gate layer is over the epitaxial layer.

Abstract: A power semiconductor device includes a substrate, an epitaxy layer, a source electrode, and a first metal layer. The substrate includes an active region, a buffer region, and a termination region. The buffer region surrounds the active region, and the termination region surrounds the active region. The epitaxy layer is located on the substrate. The epitaxy layer is located in the active region, the buffer region, and the termination region. The epitaxy layer has a first conductive type. The source electrode is located in the active region. The first metal layer is located in the buffer region. The first metal layer is connected to the source electrode.

Abstract: A virtual reality tracker includes a first part and a second part. The first part includes a plurality of first light-emitting diodes (LEDs) and an inner measurement unit (IMU). The inertial measurement unit is used for measuring the acceleration and the triaxial angular velocity of the first part. The second part includes a plurality of second light-emitting diodes. Moreover, the first part and the second part are connected by a flexible component.

Abstract: A memory chip includes a memory cell circuit, a periphery circuit, an interconnect structure, and a control logic circuit. The periphery circuit is positioned under the memory cell circuit and electrically connected to the memory cell circuit. The interconnect structure is positioned on a side surface of the memory cell circuit. The control logic circuit is positioned under the interconnect structure. The control logic circuit is electrically connected to the interconnect structure and the periphery circuit and includes a dynamic random-access memory.

Abstract: A light-emitting diode display device and a light-emission control method thereof are provided. The light-emitting diode display device includes a timing controller, multiple display pixels, and a scanning circuit. The display pixels form multiple display rows. The scanning circuit generates multiple scan signals and multiple light-emission signals that respectively drive the display rows. During a first data-writing time period of a first frame period, the timing controller provides multiple writing data to be respectively written into the display rows. During a light-emitting time period, the scanning circuit drives each of the light-emission signals to generate multiple pulses periodically according to a set period to drive the corresponding display rows. The light-emitting time period is after the first data-writing time period and before a second data-writing time period of a second frame period ends.

Abstract: A light-emitting diode display device and a light-emission control method thereof are provided. The light-emitting diode display device includes a timing controller, multiple display pixels, and a scanning circuit. The display pixels form multiple display rows. The scanning circuit generates multiple scan signals and multiple light-emission signals that respectively drive the display rows. During a first data-writing time period of a first frame period, the timing controller provides multiple writing data to be respectively written into the display rows. During a light-emitting time period, the scanning circuit drives each of the light-emission signals to generate multiple pulses periodically according to a set period to drive the corresponding display rows. The light-emitting time period is after the first data-writing time period and before a second data-writing time period of a second frame period ends.