Patents by Inventor Yan-Ru Su

Yan-Ru Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12127405
    Abstract: A three-dimensional AND flash memory device includes a stack structure, a channel pillar, a first conductive pillar and a second conductive pillar, and a charge storage structure. The stack structure is located on a dielectric substrate and includes gate layers and insulating layers alternately stacked with each other. The channel pillar extends through the stack structure. The first conductive pillar and the second conductive pillar are located in and electrically connected with the channel pillar. The first conductive pillar includes a first metal silicide pillar, and the second conductive pillar includes a second metal silicide pillar. The charge storage structure is located between the gate layers and the channel pillar.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: October 22, 2024
    Assignee: MACRONIX International Co., Ltd.
    Inventor: Yan-Ru Su
  • Publication number: 20240298442
    Abstract: A memory device includes a substrate, a stacked structure, a separation wall, first and second through vias. The substrate includes a memory array region and a staircase region. The stacked structure is located on the substrate in the memory array region and the staircase region. The stacked structure includes conductive layers and insulating layers stacked alternately. The separation wall extends through the stacked structure and divides the stacked structure into first and second blocks. The first through vias are in the first block of the staircase region. The second through vias are in the second block of the staircase region and adjacent to the first through vias. The number of layers of the stacked structure penetrated by the first through vias is smaller than the number of layers of the stacked structure penetrated by the second through vias. The memory device may be applied in a 3D AND flash memory.
    Type: Application
    Filed: March 2, 2023
    Publication date: September 5, 2024
    Applicant: MACRONIX International Co., Ltd.
    Inventor: Yan-Ru Su
  • Publication number: 20240081058
    Abstract: A memory device includes a stack structure, a channel pillar, a first conductive pillar, a second conductive pillar, a charge storage structure, a first conductive layer, a second conductive layer, and an insulating liner layer. The stack structure is located on a dielectric substrate and includes gate layers and insulating layers alternately stacked with each other. The channel pillar extends through the stack structure. The first conductive pillar and the second conductive pillar are located in and electrically connecting with the channel pillars. The charge storage structure is located between the gate layers and the channel pillar. The first conductive and the second conductive layers are located between the stack structure and the dielectric substrate. The second conductive layer is closer the channel layer than the first conductive layer. The insulating liner layer separates the second conductive layer from the channel layer and the first conductive layer.
    Type: Application
    Filed: September 7, 2022
    Publication date: March 7, 2024
    Applicant: MACRONIX International Co., Ltd.
    Inventor: Yan-Ru Su
  • Publication number: 20230262979
    Abstract: A memory device includes a dielectric substrate, a conductive layer, a gate stack structure, a plurality of ring-shaped slits and a plurality of inner slits. The conductive layer is located on the dielectric substrate. The gate stack structure is located on a first part of the conductive layer. The dielectric layer is located on the gate stack structure and a second part of the conductive layer. The plurality of ring-shaped slits extends through the dielectric layer, the gate stack structure and the conductive layer to define a plurality of tiles. The plurality of inner slits are arranged in the ring-shaped slits to define a plurality of blocks in each ring-shaped slit. A height of the plurality of inner slits is the same as a height of the plurality of ring-shaped slits.
    Type: Application
    Filed: February 17, 2022
    Publication date: August 17, 2023
    Applicant: MACRONIX International Co., Ltd.
    Inventor: Yan-Ru Su
  • Publication number: 20230217654
    Abstract: A three-dimensional AND flash memory device includes a stack structure, a channel pillar, a first conductive pillar and a second conductive pillar, and a charge storage structure. The stack structure is located on a dielectric substrate and includes gate layers and insulating layers alternately stacked with each other. The channel pillar extends through the stack structure. The first conductive pillar and the second conductive pillar are located in and electrically connected with the channel pillar. The first conductive pillar includes a first metal silicide pillar, and the second conductive pillar includes a second metal silicide pillar. The charge storage structure is located between the gate layers and the channel pillar.
    Type: Application
    Filed: January 6, 2022
    Publication date: July 6, 2023
    Applicant: MACRONIX International Co., Ltd.
    Inventor: Yan-Ru Su