Patents by Inventor Yan Solihin

Yan Solihin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11281545
    Abstract: Lazy Persistency (LP), a software persistency method that allows caches to slowly send dirty blocks to the non-volatile main memory (NVMM) through natural evictions. With LP, there are no additional writes to NVMM, no decrease in write endurance, and no performance degradation from cache line flushes and barriers. Persistency failures are discovered using software error detection (checksum), and the system recovers from them by recomputing inconsistent results. LP was evaluated and compared to the state-of-the-art Eager Persistency technique from prior work. Compared to Eager Persistency, LP reduces the execution time and write amplification overheads from 9% and 21% to only 1% and 3%, respectively.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: March 22, 2022
    Assignee: University of Central Florida Research Foundation, Inc.
    Inventors: Yan Solihin, Mohammad Alshboul, James Tuck
  • Patent number: 10956331
    Abstract: Techniques described herein generally include methods and systems related to cache partitioning in a chip multiprocessor. Cache-partitioning for a single thread or application between multiple data sources improves energy or latency efficiency of a chip multiprocessor by exploiting variations in energy cost and latency cost of the multiple data sources. Partition sizes for each data source may be selected using an optimization algorithm that minimizes or otherwise reduces latencies or energy consumption associated with cache misses.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: March 23, 2021
    Assignee: Empire Technology Development LLC
    Inventor: Yan Solihin
  • Publication number: 20200081802
    Abstract: Lazy Persistency (LP), a software persistency method that allows caches to slowly send dirty blocks to the non-volatile main memory (NVMM) through natural evictions. With LP, there are no additional writes to NVMM, no decrease in write endurance, and no performance degradation from cache line flushes and barriers. Persistency failures are discovered using software error detection (checksum), and the system recovers from them by recomputing inconsistent results. LP was evaluated and compared to the state-of-the-art Eager Persistency technique from prior work. Compared to Eager Persistency, LP reduces the execution time and write amplification overheads from 9% and 21% to only 1% and 3%, respectively.
    Type: Application
    Filed: September 9, 2019
    Publication date: March 12, 2020
    Inventors: Yan Solihin, Mohammad Alshboul, James Tuck
  • Publication number: 20190370175
    Abstract: Techniques described herein generally include methods and systems related to cache partitioning in a chip multiprocessor. Cache-partitioning for a single thread or application between multiple data sources improves energy or latency efficiency of a chip multiprocessor by exploiting variations in energy cost and latency cost of the multiple data sources. Partition sizes for each data source may be selected using an optimization algorithm that minimizes or otherwise reduces latencies or energy consumption associated with cache misses.
    Type: Application
    Filed: June 21, 2019
    Publication date: December 5, 2019
    Applicant: Empire Technology Development LLC
    Inventor: Yan Solihin
  • Patent number: 10445131
    Abstract: A processor may comprise a plurality of cores operating at heterogeneous frequencies communicatively coupled by a network of routers also operating at heterogeneous frequencies. A core may be prioritized for thread execution based on operating frequencies of routers on a path from the core to a memory controller. Relatively higher priority may be assigned to cores having a path comprising only routers operating at a relatively higher frequency. A combined priority for thread execution may be based on core frequency, router frequency, and the frequency of routers on a path from the core to a memory controller. A core may be selected based primarily on core operating frequency when cache misses fall below a threshold value.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: October 15, 2019
    Assignee: Empire Technology Development LLC
    Inventor: Yan Solihin
  • Patent number: 10445287
    Abstract: Techniques described herein generally include methods and systems related to circuit switching in a network-on-chip. According to embodiments of the disclosure, a network-on-chip may include routers configured to pre-reserve circuit-switched connections between a source node and a destination node before requested data are available for transmission from the source node to the destination node. Because the circuit-switched connection is already established between the source node and the destination node when the requested data are available for transmission from the source node, the data can be transmitted without the delay or with reduced delay caused by setup overhead of the circuit-switched connection. A connection setup message may be transmitted together with a memory request from the destination node to facilitate pre-reservation of the circuit-switched connection.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: October 15, 2019
    Assignee: Empire Technology Development LLC
    Inventor: Yan Solihin
  • Patent number: 10346227
    Abstract: Techniques described herein generally include methods and systems related to designing and operating a DRAM device that has significantly reduced refresh energy use. A method for designing a DRAM optimizes or otherwise improves the DRAM for energy efficiency based on a measured or predicted failure probability of memory cells in the DRAM. The DRAM may be configured to operate at an increased refresh interval, thereby reducing DRAM refresh energy but causing a predictable portion of the memory cells in the DRAM to leak electrical energy too quickly to retain data. The DRAM is further configured with a selected number of spare memory cells for replacing the “leaky” memory cells, so that operation of the DRAM at the increased refresh interval may result in little or no reduction in capacity of the DRAM.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: July 9, 2019
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Yan Solihin
  • Patent number: 10346308
    Abstract: Techniques described herein generally include methods and systems related to cache partitioning in a chip multiprocessor. Cache-partitioning for a single thread or application between multiple data sources improves energy or latency efficiency of a chip multiprocessor by exploiting variations in energy cost and latency cost of the multiple data sources. Partition sizes for each data source may be selected using an optimization algorithm that minimizes or otherwise reduces latencies or energy consumption associated with cache misses.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: July 9, 2019
    Assignee: Empire Technology Development LLC
    Inventor: Yan Solihin
  • Patent number: 10289452
    Abstract: Methods and systems to assign threads in a multi-core processor are disclosed. A method to assign threads in a multi-core processor may include determining data relating to memory controllers fetching data in response to cache misses experienced by a first core and a second core. Threads may be assigned to cores based on the number of cache misses processed by respective memory controllers. Methods may further include determining that a thread is latency-bound or bandwidth-bound. Threads may be assigned to cores based on the determination of the thread as latency-bound or bandwidth-bound. In response to the assignment of the threads to the cores, data for the thread may be stored in the assigned cores.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: May 14, 2019
    Assignee: Empire Technology Development, LLC
    Inventor: Yan Solihin
  • Patent number: 10176107
    Abstract: Techniques described herein generally include methods and systems related to dynamic cache-sizing used to reduce the energy consumption of a DRAM cache in a chip multiprocessor. Dynamic cache sizing may be performed by adjusting the refresh interval of a DRAM cache or by combining way power-gating of the DRAM cache with adjusting the refresh interval.
    Type: Grant
    Filed: March 29, 2014
    Date of Patent: January 8, 2019
    Assignee: Empire Technology Development LLC
    Inventor: Yan Solihin
  • Patent number: 10152410
    Abstract: Technologies are generally described manage MRAM cache writes in processors. In some examples, when a write request is received with data to be stored in an MRAM cache, the data may be evaluated to determine whether the data is to be further processed. In response to a determination that the data is to be further processed, the data may be stored in a write cache associated with the MRAM cache. In response to a determination that the data is not to be further processed, the data may be stored in the MRAM cache.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: December 11, 2018
    Assignee: Empire Technology Development LLC
    Inventor: Yan Solihin
  • Patent number: 10007605
    Abstract: A computing system to compress an array using hardware-based compression and to perform various instructions on the compressed array is generally described. The computing system may receive an instruction adapted to access an address in an array. The computing system may determine whether the address is compressible. If the address is compressible, then the computing system may determine a compressed address of a compressed array based on the address. The compressed array may represent a compressed layout of the array, where a reduced size of each compressed element in the compressed array is smaller than an original size of each element in the array. The computing system may access the compressed array at the compressed address in accordance with the instruction.
    Type: Grant
    Filed: September 20, 2015
    Date of Patent: June 26, 2018
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Yan Solihin
  • Patent number: 9990293
    Abstract: Techniques described herein generally include methods and systems related to improving energy efficiency in a chip multiprocessor by reducing the energy consumption of a DRAM cache for such a multi-chip processor. Methods of varying refresh interval may be used to improve the energy efficiency of such a DRAM cache. Specifically, a per-set refresh interval based on retention time of memory blocks in the set may be determined, and, starting from the leakiest memory block, memory blocks stored in the DRAM cache that are associated with data also stored in a lower level of cache are not refreshed.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: June 5, 2018
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Yan Solihin
  • Patent number: 9965385
    Abstract: Technologies are generally described for methods and systems effective to implement a memory allocation accelerator. A processor may generate a request for allocation of a requested chunk of memory. The request may be received by a memory allocation accelerator configured to be in communication with the processor. The memory allocation accelerator may process the request to identify an address for a particular chunk of memory corresponding to the request and may return the address to the processor.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: May 8, 2018
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Yan Solihin
  • Patent number: 9946647
    Abstract: A cache coherence mechanism may comprise a bit-to-cache map for processor cores operable up to a maximum frequency for cores of a multicore processor. Entries in a cache coherence directory may include a bit field identifying cores operable at or near the maximum frequency that share a memory block corresponding to the entry. An additional field may indicate sharing by cores operating at lower frequencies. The additional field may be indicative of the bit-field corresponding to a bit-to-cache map representative of cores other than those operating at or near the maximum frequency.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: April 17, 2018
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Yan Solihin
  • Patent number: 9916255
    Abstract: Technologies are generally described for methods and systems effective to store data in a memory module. The memory module may include a volatile portion and a non-volatile portion. The methods may comprise receiving, by a processor, a request to store the data. The request may include an indication of a virtual address. The methods may further include determining, by the processor, a persistency of the data based on the virtual address. The methods may further include performing a first operation of identifying a particular portion of the memory module based on the virtual address. The methods may further include generating a command to store the data in the particular portion of the memory module. The methods may further include controlling the operating system to perform a second operation of updating a translation lookaside buffer to indicate the persistency of the data.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: March 13, 2018
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Yan Solihin
  • Patent number: 9858111
    Abstract: Technologies are generally described for systems, devices and methods relating to multicore processors. The multicore processors may include first and second tiles with first and second caches, respectively. The first cache may include first magnetoresistive random access memory (MRAM) cells with first storage characteristics. The second cache may include second MRAM cells with second storage characteristics different from the first storage characteristics. In some examples, an interconnect structure may be coupled to the first and second tiles and may be configured to provide communication between the first tile and the second tile. Methods for handling migration between tiles and cores are also described.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: January 2, 2018
    Assignee: EMPIRE TECHNOLOGIES DEVELOPMENT LLC
    Inventor: Yan Solihin
  • Patent number: 9846627
    Abstract: Systems and methods for modeling memory access behavior and memory traffic timing behavior are disclosed. According to an aspect, a method includes receiving data indicative of memory access behavior resulting from instructions executed on a processor. The method also includes determining a statistical profile of the memory access behavior, the profile including tuple statistics of memory access behavior. Further, the method includes generating a clone of the executed instructions based on the statistical profile for use in simulating the memory access behavior.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: December 19, 2017
    Assignee: North Carolina State University
    Inventors: Yan Solihin, Yipeng Wang, Amro Awad
  • Patent number: 9772950
    Abstract: Technologies are generally described for methods and systems effective to maintain coherence in a multi-core processor on a die. In an example, a method for processing a request for a particular block in a particular region may include analyzing, by a first processor, a first cache to determine whether there is a block indicator in the first cache associated with the particular block. The method may further include when the first processor determines that the block indicator is not present in the first cache, analyzing, by the first processor, the first cache to determine whether there is a region indicator associated with the particular region. The method may further include when the first processor determines that the region indicator is not present in the first cache, the method further includes sending, by the first processor, the request to the directory in the tile.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: September 26, 2017
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Yan Solihin
  • Patent number: 9766681
    Abstract: A method is provided for each router to individually manage retransmissions at run time in a single chip computer die or a single computer that includes cores or compute nodes and routers that interconnect the cores or the compute nodes. Each router compares static energy saving and dynamic energy increase from turning off a retransmission buffer of the router in a monitoring phase. When the static energy saving is greater than the dynamic energy increase, the router turns off the retransmission buffer in a subsequent monitoring phase. When the static energy saving is less than the dynamic energy increase, the router turns on the retransmission buffer in the subsequent monitoring phase.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: September 19, 2017
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventors: Yan Solihin, Ahmad Samih