Patents by Inventor Yan-Zuo Tsai
Yan-Zuo Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250070045Abstract: In a package device, wherein integrated circuit devices are bonded to a substrate, stress arising from mechanical strain, CTE mismatch, and the like can be alleviated or eliminated by incorporating stress buffering air gaps into a protective material, such as a gap fill oxide. The air gaps can be formed by tuning and changing deposition parameters during the deposition process and/or by tuning the size and placement of adjacent integrated circuit devices in the package, and/or by forming trenches in the protective material prior to the bonding process.Type: ApplicationFiled: January 3, 2024Publication date: February 27, 2025Inventors: Ming-Tsu Chung, Yung-Chi Lin, Yan-Zuo Tsai, Yang-Chih Hsueh
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Publication number: 20250062204Abstract: A package includes a first die over and bonded to a first side of a second die, where the second die includes a first substrate, a first interconnect structure over the first substrate, a seal ring disposed within the first interconnect structure, first dummy through substrate vias (TSVs) extending through edge regions of the first substrate of the second die and in physical contact with the seal ring, and functional TSVs extending through a central region of the first substrate of the second die.Type: ApplicationFiled: January 4, 2024Publication date: February 20, 2025Inventors: Yan-Zuo Tsai, Ming-Tsu Chung, Yang-Chih Hsueh, Yung-Chi Lin
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Publication number: 20250062247Abstract: A method includes depositing a dielectric layer on a package component having a first warpage, and performing an implantation process to implant the dielectric layer with a stress modulation dopant. After the implantation process, the package component has a second warpage smaller than the first warpage.Type: ApplicationFiled: November 7, 2023Publication date: February 20, 2025Inventors: Yang-Chih Hsueh, Yan-Zuo Tsai, Ming-Tsu Chung, Yung-Chi Lin
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Publication number: 20250062136Abstract: A method includes bonding a device die onto a package component. The device die includes a semiconductor substrate, and a through-via extending into the semiconductor substrate. The method further includes depositing a dielectric liner lining sidewalls of the device die, depositing a dielectric layer on the dielectric liner, and planarizing the dielectric layer and the device die. Remaining portions of the dielectric liner and the dielectric layer form a gap-filling region, and a top end of the through-via is revealed. An implantation process is performed to introduce a stress modulation dopant into at least one of the dielectric liner and the dielectric layer. A redistribution line is formed over and electrically connecting to the through-via.Type: ApplicationFiled: November 20, 2023Publication date: February 20, 2025Inventors: Ming-Tsu Chung, Yung-Chi Lin, Yan-Zuo Tsai, Yang-Chih Hsueh, Ming-Shih Yeh
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Publication number: 20250006677Abstract: A method includes depositing a first dielectric layer as a first surface layer of a first package component, forming a plurality of metal pads in the first dielectric layer, depositing a second dielectric layer as a second surface layer of a second package component, and bonding the second package component to the first package component. The first dielectric layer is bonded to the second dielectric layer. At a time after the bonding, a metal pad in the plurality of metal pads has a top surface contacting a bottom surface of the second dielectric layer.Type: ApplicationFiled: June 27, 2023Publication date: January 2, 2025Inventors: Ming-Tsu Chung, Yung-Chi Lin, Yan-Zuo Tsai
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Publication number: 20240321694Abstract: A semiconductor device includes a first die. The first die includes a first dielectric bonding layer thereon and a plurality of first dielectric bonding patterns in the first dielectric bonding layer. A composition of the first dielectric bonding patterns is different from a composition of the first dielectric bonding layer.Type: ApplicationFiled: March 20, 2023Publication date: September 26, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chi Lin, Ming-Tsu Chung, Yan-Zuo Tsai
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Publication number: 20240274461Abstract: A die bonding tool having a tool head including a plurality of openings fluidly coupled to a vacuum source to selectively secure a semiconductor die onto the tool head via the application of a suction force. The plurality of openings have non-uniform cross-sectional areas, including one or more first openings having a first cross-sectional area and one or more second openings having a second cross-sectional area that is greater than the first cross-section area. A first minimum offset distance between each of the first openings and any peripheral edge of the tool head is less than a second minimum offset distance between each of the second openings and any peripheral edge of the tool head. The configuration of the openings in the tool head may improve bonding of the semiconductor die to a substrate by inhibiting air becoming trapped between the semiconductor die and the substrate during the bonding process.Type: ApplicationFiled: February 15, 2023Publication date: August 15, 2024Inventors: Chia-Yin CHEN, I-Chun HSU, Yu-Sheng LIN, Yan-Zuo TSAI, Yung-Chi LIN, Tsang-Jiuh WU, Wen-Chih CHIOU
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Publication number: 20240170320Abstract: A die bonding device is provided to pick up a die and place the die on a carrier. The die bonding device includes a pick-and-placer and a vacuum generator. The pick-and-placer includes an adsorption surface, a first channel and a second channel, and the first channel and the second channel are not connected to each other. The vacuum generator includes a first vacuum pump and a second vacuum pump, the first vacuum pump is connected to the first channel via a pipeline, the second vacuum pump is connected to the second channel via another pipeline, the first vacuum pump and the second vacuum pump make the pick-and-placer adsorb the die to the adsorption surface during a vacuum holding period, and the first vacuum pump and the second vacuum pump respectively make the pick-and-placer release the die to the carrier sequentially in a vacuum release period.Type: ApplicationFiled: January 19, 2023Publication date: May 23, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yan-Zuo TSAI, Yang-Chih HSUEH, Yung-Chi LIN
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Patent number: 11948920Abstract: Provided are a semiconductor device and a method for manufacturing the same, and a semiconductor package. The semiconductor device includes a die stack and a cap substrate. The die stack includes a first die, second dies stacked on the first die, and a third die stacked on the second dies. The first die includes first through semiconductor vias. Each of the second dies include second through semiconductor vias. The third die includes third through semiconductor vias. The cap substrate is disposed on the third die of the die stack. A sum of a thickness of the third die and a thickness of the cap substrate ranges from about 50 ?m to about 80 ?m.Type: GrantFiled: August 30, 2021Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-Chun Hsu, Yan-Zuo Tsai, Chia-Yin Chen, Yang-Chih Hsueh, Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou
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Publication number: 20230063851Abstract: Provided are a semiconductor device and a method for manufacturing the same, and a semiconductor package. The semiconductor device includes a die stack and a cap substrate. The die stack includes a first die, second dies stacked on the first die, and a third die stacked on the second dies. The first die includes first through semiconductor vias. Each of the second dies include second through semiconductor vias. The third die includes third through semiconductor vias. The cap substrate is disposed on the third die of the die stack. A sum of a thickness of the third die and a thickness of the cap substrate ranges from about 50 ?m to about 80 ?m.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-Chun Hsu, Yan-Zuo Tsai, Chia-Yin Chen, Yang-Chih Hsueh, Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou
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Patent number: 10867831Abstract: A method and apparatus for bonding semiconductor devices are disclosed. In an embodiment, the method may include attaching a first die to a flip head of a flip module, flipping the first die with the flip module, removing the first die from the flip module after flipping the first die, inspecting the flip head of the flip module for contamination after removing the first die, cleaning the flip head with an in situ cleaning module after inspecting the flip head, and attaching a second die to the flip head after cleaning the flip head.Type: GrantFiled: August 14, 2020Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yan-Zuo Tsai, Yang-Chih Hsueh, Chia-Yin Chen, Fu-Kang Tien, Ebin Liao, Wen-Chih Chiou
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Publication number: 20200373185Abstract: A method and apparatus for bonding semiconductor devices are disclosed. In an embodiment, the method may include attaching a first die to a flip head of a flip module, flipping the first die with the flip module, removing the first die from the flip module after flipping the first die, inspecting the flip head of the flip module for contamination after removing the first die, cleaning the flip head with an in situ cleaning module after inspecting the flip head, and attaching a second die to the flip head after cleaning the flip head.Type: ApplicationFiled: August 14, 2020Publication date: November 26, 2020Inventors: Yan-Zuo Tsai, Yang-Chih Hsueh, Chia-Yin Chen, Fu-Kang Tien, Ebin Liao, Wen-Chih Chiou
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Patent number: 10748803Abstract: A method and apparatus for bonding semiconductor devices are disclosed. In an embodiment, the method may include attaching a first die to a flip head of a flip module, flipping the first die with the flip module, removing the first die from the flip module after flipping the first die, inspecting the flip head of the flip module for contamination after removing the first die, cleaning the flip head with an in situ cleaning module after inspecting the flip head, and attaching a second die to the flip head after cleaning the flip head.Type: GrantFiled: April 22, 2019Date of Patent: August 18, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yan-Zuo Tsai, Yang-Chih Hsueh, Chia-Yin Chen, Fu-Kang Tien, Ebin Liao, Wen-Chih Chiou
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Publication number: 20190244851Abstract: A method and apparatus for bonding semiconductor devices are disclosed. In an embodiment, the method may include attaching a first die to a flip head of a flip module, flipping the first die with the flip module, removing the first die from the flip module after flipping the first die, inspecting the flip head of the flip module for contamination after removing the first die, cleaning the flip head with an in situ cleaning module after inspecting the flip head, and attaching a second die to the flip head after cleaning the flip head.Type: ApplicationFiled: April 22, 2019Publication date: August 8, 2019Inventors: Yan-Zuo Tsai, Yang-Chih Hsueh, Chia-Yin Chen, Fu-Kang Tien, Ebin Liao, Wen-Chih Chiou
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Patent number: 10269611Abstract: A method and apparatus for bonding semiconductor devices are disclosed. In an embodiment, the method may include attaching a first die to a flip head of a flip module, flipping the first die with the flip module, removing the first die from the flip module after flipping the first die, inspecting the flip head of the flip module for contamination after removing the first die, cleaning the flip head with an in situ cleaning module after inspecting the flip head, and attaching a second die to the flip head after cleaning the flip head.Type: GrantFiled: March 19, 2018Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yan-Zuo Tsai, Yang-Chih Hsueh, Chia-Yin Chen, Fu-Kang Tien, Ebin Liao, Wen-Chih Chiou
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Publication number: 20060179887Abstract: A mold for press-molding glass elements is disclosed, which comprises a substrate and a protective film; wherein the protective film, being arranged on the substrate, is made of molybdenum-ruthenium (Mo—Ru) alloy instead of those precious metal alloys such as platinum-iridium (Pt—Ir) alloy, iridium-rhenium (Ir—Re) alloy and iridium- ruthenium (Ir—Ru) alloy, etc., being used as the protective film of prior-art molds. According, the mold of the invention can be manufactured at a comparatively lower cost while is capable of being used for press-molding glass elements of high precision and high softening point.Type: ApplicationFiled: July 27, 2005Publication date: August 17, 2006Inventors: James Lung, Jenq-Gong Duh, Kuan-Ting Liu, Yan-Zuo Tsai