Patents by Inventor Yanai DANAN
Yanai DANAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11474821Abstract: In an approach to processor dependency-aware instruction execution, responsive to a new instruction being issued to an instruction issue queue in a processor, a future dependency count is incremented for each instruction of a plurality of instructions in the instruction issue queue that has a dependency on the new instruction. The plurality of instructions in the instruction issue queue are prioritized based on the future dependency count. The highest priority instruction of the plurality of instructions in the instruction issue queue is issued.Type: GrantFiled: May 12, 2021Date of Patent: October 18, 2022Assignee: International Business Machines CorporationInventors: Amir Turi, Avraham Ayzenfeld, Gilad Shimon Merran, Yanai Danan, Amit Shay, Yossi Shapira, Yair Fried, Oren Ben Gigi, Omri Rafaeli
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Patent number: 10949593Abstract: A method of performing transistor simulation with improved sensitivity to parasitic by model order reduction in transistor-level timing is disclosed. The method includes reducing a number of derivative calculations during transistor simulation by representing parasitics as a reduced-order model, wherein the reducing includes: compressing the parasitics to a reduced-order model; simulating with load which is replaced with the reduced-order model; differentiating results of the simulation with respect to reduced-order model parameters; differentiating parameters of the reduced-order model with respect to parasitic values; differentiating the parasitic values with respect to statistical parameters; and computing the differential results of the simulation with respect to the statistical parameters via chain ruling.Type: GrantFiled: July 12, 2019Date of Patent: March 16, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert J. Allen, Yanai Danan, Vasant Rao, Jeffrey P. Soreff, Xin Zhao
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Publication number: 20190332735Abstract: A method of performing transistor simulation with improved sensitivity to parasitic by model order reduction in transistor-level timing is disclosed. The method includes reducing a number of derivative calculations during transistor simulation by representing parasitics as a reduced-order model, wherein the reducing includes: compressing the parasitics to a reduced-order model; simulating with load which is replaced with the reduced-order model; differentiating results of the simulation with respect to reduced-order model parameters; differentiating parameters of the reduced-order model with respect to parasitic values; differentiating the parasitic values with respect to statistical parameters; and computing the differential results of the simulation with respect to the statistical parameters via chain ruling.Type: ApplicationFiled: July 12, 2019Publication date: October 31, 2019Inventors: Robert J. ALLEN, Yanai DANAN, Vasant RAO, Jeffrey P. SOREFF, Xin ZHAO
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Patent number: 10394986Abstract: A method of performing transistor simulation with improved sensitivity to parasitic by model order reduction in transistor-level timing is disclosed. The method includes reducing a number of derivative calculations during transistor simulation by representing parasitics as a reduced-order model, wherein the reducing includes: compressing the parasitics to a reduced-order model; simulating with load which is replaced with the reduced-order model; differentiating results of the simulation with respect to reduced-order model parameters; differentiating parameters of the reduced-order model with respect to parasitic values; differentiating the parasitic values with respect to statistical parameters; and computing the differential results of the simulation with respect to the statistical parameters via chain ruling.Type: GrantFiled: May 25, 2018Date of Patent: August 27, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert J. Allen, Yanai Danan, Vasant Rao, Jeffrey P. Soreff, Xin Zhao
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Publication number: 20180373830Abstract: A method of performing transistor simulation with improved sensitivity to parasitic by model order reduction in transistor-level timing is disclosed. The method includes reducing a number of derivative calculations during transistor simulation by representing parasitics as a reduced-order model, wherein the reducing includes: compressing the parasitics to a reduced-order model; simulating with load which is replaced with the reduced-order model; differentiating results of the simulation with respect to reduced-order model parameters; differentiating parameters of the reduced-order model with respect to parasitic values; differentiating the parasitic values with respect to statistical parameters; and computing the differential results of the simulation with respect to the statistical parameters via chain ruling.Type: ApplicationFiled: May 25, 2018Publication date: December 27, 2018Inventors: Robert J. ALLEN, Yanai DANAN, Vasant RAO, Jeffrey P. SOREFF, Xin ZHAO
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Patent number: 10031988Abstract: A method of performing transistor simulation with improved sensitivity to parasitic by model order reduction in transistor-level timing is disclosed. The method includes reducing a number of derivative calculations during transistor simulation by representing parasitics as a reduced-order model, wherein the reducing includes: compressing the parasitics to a reduced-order model; simulating with load which is replaced with the reduced-order model; differentiating results of the simulation with respect to reduced-order model parameters; differentiating parameters of the reduced-order model with respect to parasitic values; differentiating the parasitic values with respect to statistical parameters; and computing the differential results of the simulation with respect to the statistical parameters via chain ruling.Type: GrantFiled: September 24, 2014Date of Patent: July 24, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert J. Allen, Yanai Danan, Vasant Rao, Jeffrey P. Soreff, Xin Zhao
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Publication number: 20160364519Abstract: Examples of techniques for analyzing and generating timing reports for circuits are described herein. A computer-implemented method includes splitting a netlist or cross section of a circuit into sub-circuits. The method further includes building a timing graph by combining generated timing models of the sub-circuits. The method includes determining a full set of dependencies based on each sub-circuit's dependent configuration parameters. The method also further includes generating a sample plan for each sub-circuit. The method includes receiving results from a simulation for each sub-circuit based on the sample plan for each sub-circuit. The method includes generating algebraic forms for an early delay, a late delay, and a slew by curve fitting across the configuration parameters. The method includes propagating arrival times and slew in algebraic forms throughout the timing graph. The method includes evaluating checks based on selected projections from the timing graph to find a worst slack configuration.Type: ApplicationFiled: June 11, 2015Publication date: December 15, 2016Inventors: Robert J. Allen, Yanai Danan, Vasant B. Rao, Xin Zhao
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Patent number: 9501608Abstract: Examples of techniques for analyzing and generating timing reports for circuits are described herein. A computer-implemented method includes splitting a netlist or cross section of a circuit into sub-circuits. The method further includes building a timing graph by combining generated timing models of the sub-circuits. The method includes determining a full set of dependencies based on each sub-circuit's dependent configuration parameters. The method also further includes generating a sample plan for each sub-circuit. The method includes receiving results from a simulation for each sub-circuit based on the sample plan for each sub-circuit. The method includes generating algebraic forms for an early delay, a late delay, and a slew by curve fitting across the configuration parameters. The method includes propagating arrival times and slew in algebraic forms throughout the timing graph. The method includes evaluating checks based on selected projections from the timing graph to find a worst slack configuration.Type: GrantFiled: June 11, 2015Date of Patent: November 22, 2016Assignee: International Business Machines CorporationInventors: Robert J. Allen, Yanai Danan, Vasant B. Rao, Xin Zhao
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Publication number: 20160085890Abstract: A method of performing transistor simulation with improved sensitivity to parasitic by model order reduction in transistor-level timing is disclosed. The method includes reducing a number of derivative calculations during transistor simulation by representing parasitics as a reduced-order model, wherein the reducing includes: compressing the parasitics to a reduced-order model; simulating with load which is replaced with the reduced-order model; differentiating results of the simulation with respect to reduced-order model parameters; differentiating parameters of the reduced-order model with respect to parasitic values; differentiating the parasitic values with respect to statistical parameters; and computing the differential results of the simulation with respect to the statistical parameters via chain ruling.Type: ApplicationFiled: September 24, 2014Publication date: March 24, 2016Inventors: Robert J. ALLEN, Yanai DANAN, Vasant RAO, Jeffrey P. SOREFF, Xin ZHAO