Abstract: Embodiments of this application provide a user hearing protection method, apparatus, and electronic device. In the method, after an electronic device enables a hearing protection mode, when an audio output mode is a headset output, sound pressure output by the headset is obtained based on current-frame sound source data; when the sound pressure is greater than a predetermined sound pressure threshold, an instantaneous sound pressure over-standard warning is performed, and an instantaneous sound pressure over-standard protection operation is performed on the electronic device. In addition, after the output sound pressure is obtained, the sound pressure may be stored, and a sound dose accumulated to a current moment may be determined based on the stored historical sound pressure data; when the sound dose is greater than a predetermined sound dose standard value, sound dose over-standard warning and a sound dose over-standard protection operation are performed.

Abstract: This application provides a battery protection circuit, a battery protection board, a battery, and a terminal device. The battery protection circuit includes: a first detection unit; a second detection unit; and a current detection element, a first switch unit, and a second switch unit that are configured to connect to an electrochemical cell in series, to form a charging loop or a discharging loop. The first detection unit corresponds to the first switch unit, and the second detection unit corresponds to the second switch unit. Each detection unit controls, based on a detected voltage at two ends of the same current detection element, a corresponding switch unit to be closed or opened, so as to control the loop to be closed or opened.

Abstract: Embodiments of this application provide a user hearing protection method, apparatus, and electronic device. In the user hearing protection method, after an electronic device enables a hearing protection mode, when an audio output mode is a headset output, sound pressure output by the headset is obtained based on current-frame sound source data; when the sound pressure is greater than a predetermined sound pressure threshold, an instantaneous sound pressure over-standard warning is performed, and an instantaneous sound pressure over-standard protection operation is performed on the electronic device, and a user's hearing can be protected when the instantaneous sound pressure exceeds a standard.

Abstract: This application provides a battery protection circuit, a battery protection board, a battery, and a terminal device. The battery protection circuit includes: a first detection unit; a second detection unit; and a current detection element, a first switch unit, and a second switch unit that are configured to connect to an electrochemical cell in series, to form a charging loop or a discharging loop. The first detection unit corresponds to the first switch unit, and the second detection unit corresponds to the second switch unit. Each detection unit controls, based on a detected voltage at two ends of the same current detection element, a corresponding switch unit to be closed or opened, so as to control the loop to be closed or opened.

Abstract: Systems and methods for reducing the area and improving the performance of a non-volatile memory array are described. The non-volatile memory array may comprise a 3D NAND memory array that includes vertical NAND strings that are arranged orthogonal to a substrate. A vertical NAND string may include floating gate memory cell transistors or charge trap memory cell transistors. Sensing circuitry for sensing the programmed data states of memory cell transistors within the vertical NAND strings may be positioned underneath the 3D NAND memory array and connections from bit lines positioned above the 3D NAND memory array may be made using vertical connections extending though the 3D NAND memory array or through memory breaks within the 3D NAND memory array.

Abstract: Systems and methods for reducing the area and improving the performance of a non-volatile memory array are described. The non-volatile memory array may comprise a 3D NAND memory array that includes vertical NAND strings that are arranged orthogonal to a substrate. A vertical NAND string may include floating gate memory cell transistors or charge trap memory cell transistors. Sensing circuitry for sensing the programmed data states of memory cell transistors within the vertical NAND strings may be positioned underneath the 3D NAND memory array and connections from bit lines positioned above the 3D NAND memory array may be made using vertical connections extending though the 3D NAND memory array or through memory breaks within the 3D NAND memory array.