Patents by Inventor Yanbin XU

Yanbin XU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12269139
    Abstract: An intelligent production line for turning tool bit cavities and an application method are provided, which solve the problem that a production line in the prior art has low working efficiency. The intelligent production line has the beneficial effects of a compact arrangement structure, higher safety and improved working efficiency. The intelligent production line for turning tool bit cavities includes a robot. Material tables and at least one machining center are arranged around the robot. A transfer station used for transferring materials is arranged between the machining center and the robot. A protective fence is arranged between a position above the material tables and the robot, and between the transfer station and the robot. The robot is provided with a mechanical arm including a base plate. The base plate is provided with at least one clamping jaw and fixed with a laser detecting unit for detecting the materials.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: April 8, 2025
    Assignees: Qingdao University of Technology, Ningbo Sanhan Alloy Material Co., Ltd.
    Inventors: Changhe Li, Haogang Li, Liang Luo, Weixi Ji, Binhui Wan, Shuo Yin, Huajun Cao, Bingheng Lu, Lizhi Tang, Xin Cui, Mingzheng Liu, Yanbin Zhang, Jie Xu, Huiming Luo, Haizhou Xu, Min Yang, Huaping Hong, Teng Gao, Yuying Yang, Wuxing Ma, Shuai Chen
  • Publication number: 20250112120
    Abstract: Integrated circuit structures having deep via bar width tuning are described. For example, an integrated circuit structure includes a plurality of gate lines extending over first and second semiconductor nanowire stack channel structures or fin structures. A plurality of trench contacts is intervening with the plurality of gate lines. A conductive structure is between the first and second semiconductor nanowire stack channel structures or fin structures, the conductive structure having a first width in a first region and a second width in a second region between the first and second semiconductor nanowire stack channel structures or fin structures, the second width different than the first width.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Tao CHU, Minwoo JANG, Yanbin LUO, Paul PACKAN, Conor P. PULS, Guowei XU, Chiao-Ti HUANG, Robin CHAO, Feng ZHANG, Ting-Hsiang HUNG, Chia-Ching LIN, Yang ZHANG, Chung-Hsun LIN, Anand S. MURTHY
  • Publication number: 20250113595
    Abstract: Multiple voltage threshold integrated circuit structures with local layout effect tuning, and methods of fabricating multiple voltage threshold integrated circuit structures with local layout effect tuning, are described. For example, an integrated circuit structure includes a first fin structure or vertical arrangement of horizontal nanowires. A second fin structure or vertical arrangement of horizontal nanowires is laterally spaced apart from the first fin structure or vertical arrangement of horizontal nanowires. An N-type gate structure is over the first fin structure or vertical arrangement of horizontal nanowires. A P-type gate structure is over the second fin structure or vertical arrangement of horizontal nanowires, the P-type gate structure in contact with the N-type gate structure with a PN boundary between the P-type gate structure and the N-type gate structure.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Inventors: Tao CHU, Minwoo JANG, Yanbin LUO, Paul PACKAN, Guowei XU, Chiao-Ti HUANG, Robin CHAO, Feng ZHANG, Ting-Hsiang HUNG, Chia-Ching LIN, Yang ZHANG, Chung-Hsun LIN, Anand S. MURTHY
  • Publication number: 20250107175
    Abstract: Integrated circuit structures having reduced local layout effects, and methods of fabricating integrated circuit structures having reduced local layout effects, are described. For example, an integrated circuit structure includes an NMOS region including a first plurality of fin structures or vertical stacks of horizontal nanowires, and first alternating gate lines and trench contact structures over the first plurality of fin structures or vertical stacks of horizontal nanowires. The integrated circuit structure also includes a PMOS region including a second plurality of fin structures or vertical stacks of horizontal nanowires, and second alternating gate and trench contact structures over the second plurality of fin structures or vertical stacks of horizontal nanowires. A gate line is shared between the NMOS region and the PMOS region, and a trench contact structure is shared between the NMOS region and the PMOS region.
    Type: Application
    Filed: September 25, 2023
    Publication date: March 27, 2025
    Inventors: Tao CHU, Minwoo JANG, Yanbin LUO, Paul PACKAN, Guowei XU, Chiao-Ti HUANG, Robin CHAO, Feng ZHANG, Ting-Hsiang HUNG, Chia-Ching LIN, Yang ZHANG, Chung-Hsun LIN, Anand S. MURTHY
  • Publication number: 20250083280
    Abstract: Provided in the present invention are a dynamic collection device for an oil film and temperature distribution in a grinding zone and an operating method thereof. A spectroscope and a 45-degree flat mirror are utilized to carry out optical imaging of the permeation and infiltration of the grinding fluid in a grinding zone during a grinding process, and a video signal imported into a high-speed camera is converted into a digital signal processed by a CCD photosensitive element, and a dynamic image is imported for dynamic collection. Infrared radiation emitted from the grinding zone is reflected through the 45-degree flat mirror, and transmitted to the thermal imaging camera, and the signal is transmitted to an internal infrared detector. The infrared detector adjusts and amplifies the received signal and outputs it to an infrared thermal imaging chip. After image processing, the temperature distribution image is imported for dynamic collection.
    Type: Application
    Filed: July 19, 2023
    Publication date: March 13, 2025
    Applicant: QINGDAO UNIVERSITY OF TECHNOLOGY
    Inventors: Yanbin ZHANG, Wenyi LI, Xin CUI, Changhe LI, Zongming ZHOU, Shuaiqiang XU, Bo LIU, Yun CHEN
  • Patent number: 11282868
    Abstract: The present disclosure provides an array substrate, which includes a first signal line and a second signal line arranged on a substrate as different layers that are insulating and spaced apart from each other, wherein one end of the first signal line includes a first conductive section, one end of the second signal line includes a second conductive section, the first conductive section and the second conductive section are electrically connected through a connecting structure, and wherein orthographic projections of an area where the first conductive section is located and an area where the second conductive section is located overlap at least partially. The array substrate can reduce the possibility of occurrence of circuit break between signal lines and improve the effect of connection between different signal lines.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: March 22, 2022
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Lin Li, Yanbin Xu
  • Publication number: 20210210521
    Abstract: The present disclosure provides an array substrate, which includes a first signal line and a second signal line arranged on a substrate as different layers that are insulating and spaced apart from each other, wherein one end of the first signal line includes a first conductive section, one end of the second signal line includes a second conductive section, the first conductive section and the second conductive section are electrically connected through a connecting structure, and wherein orthographic projections of an area where the first conductive section is located and an area where the second conductive section is located overlap at least partially. The array substrate can reduce the possibility of occurrence of circuit break between signal lines and improve the effect of connection between different signal lines.
    Type: Application
    Filed: February 8, 2018
    Publication date: July 8, 2021
    Applicants: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Lin LI, Yanbin XU