Abstract: The present disclosure discloses a shift register unit and a threshold voltage compensation method thereof, a driving circuit and a display apparatus. The shift register unit includes a cascaded output circuit coupled to a pull-up node, a clock signal input terminal, and a cascaded signal output terminal. The shift register unit is configured to transmit a clock signal from the clock signal input terminal to the cascaded signal output terminal under control of the pull-up node. A compensation circuit has a voltage output terminal coupled to the pull-up node, and is configured to provide an output voltage signal through the voltage output terminal during a blanking phase of a frame. The output voltage signal drives reverse drift of a threshold voltage of the cascaded output circuit.

Abstract: A display substrate has a display area and an encapsulation area around the display area. The display substrate includes a substrate and a spacer layer. The spacer layer is located on a side of the substrate, and includes a plurality of first columnar spacers located in the encapsulation area and distributed at intervals around the display area, and bottom ends of the plurality of first columnar spacers are fixedly disposed on the substrate. Ends of the plurality of first columnar spacers proximate to the substrate are the bottom ends thereof, and ends of the plurality of first columnar spacers away from the substrate are top ends thereof.

Abstract: The present disclosure discloses a shift register unit and a threshold voltage compensation method thereof, a driving circuit and a display apparatus. The shift register unit includes a cascaded output circuit coupled to a pull-up node, a clock signal input terminal, and a cascaded signal output terminal. The shift register unit is configured to transmit a clock signal from the clock signal input terminal to the cascaded signal output terminal under control of the pull-up node. A compensation circuit has a voltage output terminal coupled to the pull-up node, and is configured to provide an output voltage signal through the voltage output terminal during a blanking phase of a frame. The output voltage signal drives reverse drift of a threshold voltage of the cascaded output circuit.

Abstract: The present disclosure provides a color film substrate and a preparation method therefor, a display device and a glue applying system. The method for preparing a color film substrate includes forming a transparent insulating layer, wherein thickness of the transparent insulating layer is determined according to thickness of a metal film layer on an array substrate that is paired with the color film substrate.

Abstract: The present disclosure provides a color film substrate and a preparation method therefor, a display device and a glue applying system. The method for preparing a color film substrate includes forming a transparent insulating layer, wherein thickness of the transparent insulating layer is determined according to thickness of a metal film layer on an array substrate that is paired with the color film substrate.

Abstract: The present disclosure discloses a method for fabricating an array substrate, including: providing a base substrate which includes a transparent substrate, a data electrode pattern layer formed on the transparent substrate, and an insulation layer covering the data electrode pattern layer, the data electrode pattern layer comprising at least one data electrode; forming a via-hole penetrating through the insulation layer so as to expose at least a part of one of the at least one data electrode; forming a transparent electrode material layer; forming a transparent electrode layer which includes a transparent electrode and a connecting portion connected to the transparent electrode, the connecting portion being located in the via-hole so as to electrically connect the transparent electrode with a corresponding data electrode, and a filling being provided above the connecting portion. The present disclosure also discloses an array substrate and a display device.

Abstract: The present disclosure discloses a method for fabricating an array substrate, including: providing a base substrate which includes a transparent substrate, a data electrode pattern layer formed on the transparent substrate, and an insulation layer covering the data electrode pattern layer, the data electrode pattern layer comprising at least one data electrode; forming a via-hole penetrating through the insulation layer so as to expose at least a part of one of the at least one data electrode; forming a transparent electrode material layer; forming a transparent electrode layer which includes a transparent electrode and a connecting portion connected to the transparent electrode, the connecting portion being located in the via-hole so as to electrically connect the transparent electrode with a corresponding data electrode, and a filling being provided above the connecting portion. The present disclosure also discloses an array substrate and a display device.

Abstract: An array substrate and a method for manufacturing the same, and a display device are provided. The method includes: forming a thin film transistor (TFT) structure of a display region and a TFT structure of the GOA region on a substrate; sequentially forming a first insulating layer, an indium tin oxide (ITO) layer and a photoresist layer on the TFT structure; exposing and developing the photoresist layer using a halftone mask plate, and etching the ITO layer, to form an electrode layer in the GOA region and an electrode layer in the display region; and ashing the remaining photoresist to completely remove the photoresist on the electrode layer in the display region and to thinning the photoresist on the electrode layer in the GOA region.

Abstract: An array substrate and a method for manufacturing the same, and a display device are provided. The method includes: forming a thin film transistor (TFT) structure of a display region and a TFT structure of the GOA region on a substrate; sequentially forming a first insulating layer, an indium tin oxide (ITO) layer and a photoresist layer on the TFT structure; exposing and developing the photoresist layer using a halftone mask plate, and etching the ITO layer, to form an electrode layer in the GOA region and an electrode layer in the display region; and ashing the remaining photoresist to completely remove the photoresist on the electrode layer in the display region and to thinning the photoresist on the electrode layer in the GOA region.

Abstract: A photoresist pre-baking method, a photoresist pre-baking device and a lithographic apparatus are disclosed. The device includes a heating plate and a temperature controller. The heating plate includes a plurality of heating units, and the heating plate is configured to heat a substrate to be baked through the plurality of heating units, and the temperature controller is electrically connected with each of the heating units, and configured to adjust a heating parameter of each of the heating units of the heating plate, the heating parameter including at least one of a heating temperature and a heating duration.