Abstract: A system for controlling power applied to pixels in an imager. A first switch coupling the internal power node of the pixels to the power supply of the imager. A second switch coupling the internal power node of the pixels to a ground potential or low potential. The first and second switches are controlled complimentary to each other during integration and readout of the pixels. A third switch providing a high impedance mode where the internal power node and n+ guard ring are isolated from the operating and ground potentials.

Abstract: A VLN biasing scheme implemented in an image sensor with top/bottom readout. A first and second current sink coupled to the top of a first column of pixels and a second column of pixels respectively. A third and fourth current sink coupled to the bottom of a first column of pixels and a second column of pixels respectively. During column readout, each current sink sinks an equal amount of current.

Abstract: Circuits and methods of generating control signals for transistors in a pixel row of a pixel array are disclosed. The circuits include a transfer transistor control signal row driver that includes a plurality of output branches and a reset transistor control signal row driver that includes a plurality of output branches. The row drivers output positive boosted control signals to selected pixel rows during a photosensor-to-floating diffusion region charge transfer phase and during a floating diffusion region reset phase and to unselected pixel rows during an initial part of an integration phase. The row drivers output positive non-boosted control signals to unselected non-integrating pixel rows.