Patents by Inventor Yanfei Sun

Yanfei Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240359972
    Abstract: Provided is a package structure, including: an insulating dielectric layer having a first surface and a second surface opposite to each other, wherein at least one first accommodation space running from the first surface to the second surface is formed in the insulating dielectric layer; and at least one conductive post in one-to-one correspondence with the at least one first accommodation space, wherein the conductive post is within the corresponding first accommodation space, a material of the conductive post comprises a non-metallic conductive material, and an absolute value of a difference between a thermal expansion coefficient of the conductive post and a thermal expansion coefficient of the insulating dielectric layer is less than or equal to 8×10?6/° C.; wherein the at least one conductive post comprises at least one first conductive post, two end faces of the first conductive post are flush with the first surface and the second surface, respectively.
    Type: Application
    Filed: July 9, 2024
    Publication date: October 31, 2024
    Inventors: Lihui WANG, Yue LI, Qiuxu WEI, Weilong GUO, Wenbo CHANG, Taonan ZHANG, Jie SUN, Nana HE, Yanfei REN, Feng QU
  • Patent number: 12119069
    Abstract: In an anti-fuse memory reading circuit with controllable reading time, a reading time control circuit generates a control signal corresponding to reading time. Based on a clock signal, a programmable reading pulse generation circuit generates a reading pulse with a pulse width corresponding to the control signal. Based on the reading pulse and the control signal, the reading amplification circuit selects a pull-up current source corresponding to the reading time, pulls up a voltage on a bit line (BL) of an anti-fuse memory cell, reads data stored in the anti-fuse memory cell starting from a rising edge of the reading pulse, and latches the read data at a falling edge of the reading pulse. The anti-fuse memory reading circuit can generate a reading pulse with a corresponding pulse width and a pull-up current source with a corresponding size based on the required reading time.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: October 15, 2024
    Assignee: WUXI ESIONTECH CO., LTD.
    Inventors: Zhengzhou Cao, Jie Zhu, Yanfei Zhang, Jing Sun, Zhenkai Ji, Zhengnan Ding
  • Patent number: 12093089
    Abstract: A generic domain compute system that is customizable for at least one domain or zone compute in a vehicle having a gateway power and control (GAPAC). The GAPAC has a power supply, a scalable microcontroller, a power management integrated circuit, a set of standardized and scalable external connectors for external inter-connections for Ethernet and car connector, a standard and scalable internal connector for internal inter-connections for power, control and generic busses. At least a first compute extension (COMEX) has a standard and scalable connecter internally connected to the GAPAC. The COMEX has a scalable microcontroller, a power management integrated circuit and a set of standardized and scalable connectors for external inter-connections. The COMEX is supplied with a permanent voltage from the GAPAC power supply. The microcontrollers, external connectors and internal connectors are scaled according to the domain or zone compute application.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: September 17, 2024
    Assignee: Harman Becker Automotive Systems GmbH
    Inventors: Günther Kraft, Krunoslav Orcic, Jibin Yuan, Andreas Koerner, Yanfei Sun, Christian Zappe, Frank Gitzinger
  • Publication number: 20220326743
    Abstract: A generic domain compute system that is customizable for at least one domain or zone compute in a vehicle having a gateway power and control (GAPAC). The GAPAC has a power supply, a scalable microcontroller, a power management integrated circuit, a set of standardized and scalable external connectors for external inter-connections for Ethernet and car connector, a standard and scalable internal connector for internal inter-connections for power, control and generic busses. At least a first compute extension (COMEX) has a standard and scalable connecter internally connected to the GAPAC. The COMEX has a scalable microcontroller, a power management integrated circuit and a set of standardized and scalable connectors for external inter-connections. The COMEX is supplied with a permanent voltage from the GAPAC power supply. The microcontrollers, external connectors and internal connectors are scaled according to the domain or zone compute application.
    Type: Application
    Filed: September 14, 2020
    Publication date: October 13, 2022
    Applicant: Harman Becker Automotive Systems GmbH
    Inventors: Günther Kraft, Krunoslav Orcic, Jibin Yuan, Andreas Koerner, Yanfei Sun, Christian Zappe, Frank Gitzinger
  • Patent number: 11036147
    Abstract: A system for estimating front side overlay on a sample based on shape data is disclosed. The system includes a characterization sub-system and a controller. The controller includes one or more processors configured to: generate a vacuum hole map of a vacuum chuck; generate a vacuum force distribution across a sample based on the generated vacuum hole map of the vacuum chuck; determine shape data of the sample based on the vacuum force distribution and an identified relationship between backside surface roughness and vacuum force of the vacuum chuck; and convert the shape data of the sample to an overlay value of a frontside surface of the sample.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: June 15, 2021
    Assignee: KLA Corporation
    Inventors: Jian Shen, Ningqi Zhu, John McCormack, Yanfei Sun
  • Publication number: 20200301291
    Abstract: A system for estimating front side overlay on a sample based on shape data is disclosed. The system includes a characterization sub-system and a controller. The controller includes one or more processors configured to: generate a vacuum hole map of a vacuum chuck; generate a vacuum force distribution across a sample based on the generated vacuum hole map of the vacuum chuck; determine shape data of the sample based on the vacuum force distribution and an identified relationship between backside surface roughness and vacuum force of the vacuum chuck; and convert the shape data of the sample to an overlay value of a frontside surface of the sample.
    Type: Application
    Filed: March 6, 2020
    Publication date: September 24, 2020
    Inventors: Jian Shen, Ningqi Zhu, John McCormack, Yanfei Sun
  • Patent number: 10374062
    Abstract: The present invention provides an array substrate, a manufacturing method thereof and a display panel. The array substrate includes a substrate and an insulation layer provided on the substrate, the insulation layer including a via therein formed by etching. The insulation layer further includes a plurality of insulation sub-layers stacked on each other, and an insulation sub-layer among the plurality of insulation sub-layers which is farther away from the substrate has a larger etching rate under an etching condition for forming the via.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: August 6, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventor: Yanfei Sun
  • Publication number: 20180097087
    Abstract: The present invention provides an array substrate, a manufacturing method thereof and a display panel. The array substrate includes a substrate and an insulation layer provided on the substrate, the insulation layer including a via therein formed by etching. The insulation layer further includes a plurality of insulation sub-layers stacked on each other, and an insulation sub-layer among the plurality of insulation sub-layers which is farther away from the substrate has a larger etching rate under an etching condition for forming the via.
    Type: Application
    Filed: May 23, 2016
    Publication date: April 5, 2018
    Inventor: Yanfei SUN
  • Publication number: 20120327303
    Abstract: A method of displaying an image defined by an input video signal on a backlit video device accommodates changes of luminance between successive frames of the input video signal. Changes of luminance distribution, which is a function of a distribution of pixel luminance values in the frames, between the successive frames are detected. Target adjustments to luminance of the backlight and to light transmission of the image panel for a current frame of the input video signal are defined to compensate luminance of the displayed image for the adjustment to luminance of the backlight. Actual adjustments to luminance of the backlight and to light transmission of the image panel for the current frame are functions of the target adjustments for the current frame and of the actual adjustments for a previous frame in proportions, which are a function of the changes detected of luminance distribution between successive frames.
    Type: Application
    Filed: June 6, 2012
    Publication date: December 27, 2012
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Yanfei Sun, Zhong Li He, Chunpeng Lu, Kevin Zhang
  • Patent number: D1004171
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: November 7, 2023
    Assignee: Shenzhen Subject Technology Co., Ltd.
    Inventor: Yanfei Sun