Abstract: A high-speed low-latency interconnect interface (HLII) for silicon interposer interconnection is provided. The HLII is configured to perform large-scale input/output (I/O) interconnection on a silicon interposer, and includes a physical link (PL) and an LL (LL). The LL receives a data signal, a configuration signal, and a control signal of logical resource inside a chiplet, and can complete data conversion, parity check, training, channel repair, instruction stream generation, and other functions for the PL. The PL receives and transmits a data signal converted by the LL. The PL includes a high-speed I/O port, a first input first output (FIFO), and related control logic. The high-speed I/O port of the PL is compatible with both a double date rate (DDR) transmission mode and a single data rate (SDR) transmission mode.

Abstract: An apparatus and a method for testing a multi-channel high-speed low-latency interconnect interface (HLII) for a silicon interposer are provided. The apparatus includes: a standard test port configured to exchange a test instruction; an asynchronous bypass port configured to directly access an input/output (I/O) port of a channel of a physical layer of the interconnection interface; a built-in self-test (BIST) engine configured to implement inter-level loopback testing and data verification; a redundant data channel configured to repair a damaged data channel; and a delay chain testing circuit configured to test a function and linearity of a delay chain. The apparatus embeds test and repair logic into the physical layer and a link layer, achieving internal test control without any external controller. In this way, a sample can be tested and quickly screened to ensure its performance.

Abstract: In an anti-fuse memory reading circuit with controllable reading time, a reading time control circuit generates a control signal corresponding to reading time. Based on a clock signal, a programmable reading pulse generation circuit generates a reading pulse with a pulse width corresponding to the control signal. Based on the reading pulse and the control signal, the reading amplification circuit selects a pull-up current source corresponding to the reading time, pulls up a voltage on a bit line (BL) of an anti-fuse memory cell, reads data stored in the anti-fuse memory cell starting from a rising edge of the reading pulse, and latches the read data at a falling edge of the reading pulse. The anti-fuse memory reading circuit can generate a reading pulse with a corresponding pulse width and a pull-up current source with a corresponding size based on the required reading time.

Abstract: A delay adjustment cell is disposed in a channel of at least one regional clock of a chip clock architecture, and the delay adjustment cell includes a plurality of parallel delay paths with different delay values. The delay adjustment cell gates one of the delay paths based on an obtained configuration signal such that a connected regional clock has a corresponding target delay, and a target delay of each regional clock corresponds to a clock skew mode of the programmable logic chip. A clock skew between different regional clocks is adjusted by controlling the gated delay path in the delay adjustment cell, such that a clock skew of the chip can be adjusted in a relatively large range. Under the same resource configuration, different path choices of the delay adjustment cell lead to different clock skews to meet different clock skew modes in different application scenarios.

Abstract: A configuration circuit of a flash FPGA for realizing external monitoring and configuration is provided. In the configuration circuit, a positive high-voltage output terminal of a positive high-voltage charge pump is connected to a positive high-voltage external monitoring port through a positive high-voltage bidirectional switch circuit, and the positive high-voltage output terminal of a positive high-voltage charge pump is further configured as a positive output end of a voltage supply circuit. A negative high-voltage output terminal of a negative high-voltage charge pump is connected to a negative high-voltage external monitoring port through a negative high-voltage bidirectional switch circuit, and the negative high-voltage output terminal of a negative high-voltage charge pump is further configured as a negative output end of the voltage supply circuit. Based on a received mode adjustment signal, a mode control circuit controls to enter an external monitoring mode or an external configuration mode.

Abstract: In an anti-fuse programming control circuit based on a master-slave charge pump structure, a master charge pump module obtains an external voltage and is connected to a plurality of slave charge pump modules. Each slave charge pump module is connected to an anti-fuse bank. The distance between the layout position of each slave charge pump module and the layout position of the connected anti-fuse bank does not exceed a predetermined distance. Based on a programming voltage output by each slave charge pump module to the connected anti-fuse bank, the feedback network outputs a feedback signal corresponding to the slave charge pump module to the master charge pump module. Based on the feedback signal corresponding to each slave charge pump module, the master charge pump module adjusts a master drive signal provided to the slave charge pump module to stabilize the programming voltage output by the slave charge pump module.

Abstract: Disclosed is a two-layer three-rail planar robot with a parallelogram, including a fixed platform, a moving platform, and three branched chains. Three planar curved rails I are provided on the fixed platform. Three planar curved rails II are fixedly connected to the moving platform. Each planar curved rail I is connected to a planar curved rail II corresponding to the planar curved rail I by one of the branched chains. Each of the branched chains includes a slider I, two connecting rods provided in parallel, a slider II. The slider I is slidably connected to the planar curved rail I. The slider I is rotatably connected to one end of each connecting rod by a revolute pair I, the other end of the connecting rod is rotatably connected to the slider II by a revolute pair II. The slider II is slidably connected to the planar curved rail II.

Abstract: The present application discloses a multi-die FPGA implementing a built-in analog circuit using an active silicon connection layer, and relates to the field of FPGA technology. The multi-die FPGA allows multiple small-scale and small-area dies to cascade to achieve large-scale and large-area FPGA products, reducing processing difficulties and improving chip production yields. Meanwhile, due to the existence of the active silicon connection layer, some circuit structures that are difficult to implement within the die and/or occupy a large die area and/or have a low processing requirement can be laid out in the silicon connection layer, solving the existing problems of making these circuit structures directly within the die. Part of the circuit structures can be implemented within the silicon connection layer and the rest in the die, which helps optimize the performance of FPGA products, improve system stability, and reduce system area.

Abstract: Disclosed are an electronic device, an expansion card assembly and a server device. The electronic device comprises a hard disk slot and the expansion card assembly. The expansion card assembly is arranged in the hard disk slot in a pluggable manner; the hard disk slot comprises a first type of interface and a second type of interface. The first type of interface is used for communicating with the hard disk, and the second type of interface is used for communicating with the expansion card assembly. Therefore, the expansion card assembly is expanded by means of the hard disk slot in the electronic device, so that the expansion requirement of the expansion card assembly is met.

Abstract: A single-layer three-section rail-type planar robot containing a double parallelogram, is composed of a stationary platform, a motion platform and three branched chains with the same structure connecting the stationary platform and the motion platform, the stationary platform is provided with three planar curved rails, each planar curved rail is connected to the motion platform through a branched chain, and each branched chain includes a slider, two link bars I arranged in parallel, two link bars II arranged in parallel, and link bar III, select one revolute joint I in each branched chain to form three revolute joints I as the main driving joint or three sliders as the driving parts.

Abstract: A high-speed low-latency interconnect interface (HLII) for silicon interposer interconnection is provided. The HLII is configured to perform large-scale input/output (I/O) interconnection on a silicon interposer, and includes a physical link (PL) and an LL (LL). The LL receives a data signal, a configuration signal, and a control signal of logical resource inside a chiplet, and can complete data conversion, parity check, training, channel repair, instruction stream generation, and other functions for the PL. The PL receives and transmits a data signal converted by the LL. The PL includes a high-speed I/O port, a first input first output (FIFO), and related control logic. The high-speed I/O port of the PL is compatible with both a double date rate (DDR) transmission mode and a single data rate (SDR) transmission mode.

Abstract: An apparatus and a method for testing a multi-channel high-speed low-latency interconnect interface (HLII) for a silicon interposer are provided. The apparatus includes: a standard test port configured to exchange a test instruction; an asynchronous bypass port configured to directly access an input/output (I/O) port of a channel of a physical layer of the interconnection interface; a built-in self-test (BIST) engine configured to implement inter-level loopback testing and data verification; a redundant data channel configured to repair a damaged data channel; and a delay chain testing circuit configured to test a function and linearity of a delay chain. The apparatus embeds test and repair logic into the physical layer and a link layer, achieving internal test control without any external controller. In this way, a sample can be tested and quickly screened to ensure its performance.

Abstract: Disclosed is a two-layer three-rail planar robot with a parallelogram, including a fixed platform, a moving platform, and three branched chains. Three planar curved rails I are provided on the fixed platform. Three planar curved rails II are fixedly connected to the moving platform. Each planar curved rail I is connected to a planar curved rail II corresponding to the planar curved rail I by one of the branched chains. Each of the branched chains includes a slider I, two connecting rods provided in parallel, a slider II. The slider I is slidably connected to the planar curved rail I. The slider I is rotatably connected to one end of each connecting rod by a revolute pair I, the other end of the connecting rod is rotatably connected to the slider II by a revolute pair II. The slider II is slidably connected to the planar curved rail II.

Abstract: A configuration control circuit of a flash-type FPGA capable of suppressing programming interference is provided. The configuration control circuit adds a programming selection circuit compared with a conventional configuration control circuit. When a programming operation is performed on a flash memory cell located in a target row and a target column, the programming selection circuit controls a path between a programming bit line (BL) voltage and a BL voltage obtaining terminal of the flash memory cell located in the target row and the target column to be turned on, and a path between the programming BL voltage and a BL voltage obtaining terminal of a flash memory cell located in another row and the target column to be turned off.

Abstract: A single-layer three-section rail-type planar robot containing a double parallelogram, is composed of a stationary platform, a motion platform and three branched chains with the same structure connecting the stationary platform and the motion platform, the stationary platform is provided with three planar curved rails, each planar curved rail is connected to the motion platform through a branched chain, and each branched chain includes a slider, two link bars I arranged in parallel, two link bars II arranged in parallel, and link bar III, select one revolute joint I in each branched chain to form three revolute joints I as the main driving joint or three sliders as the driving parts.

Abstract: The present disclosure discloses an FPGA device forming a network-on-chip by using a silicon connection layer. An active silicon connection layer is designed inside the FPGA device. A silicon connection layer interconnection framework is arranged inside the silicon connection layer. Bare die functional modules inside an FPGA bare die are connected to the silicon connection layer interconnection framework to jointly form the network-on-chip. Each bare die functional module and a network interface and a router that are in the silicon connection layer interconnection framework form an NOC node. The NOC nodes intercommunicate with each other, so that the bare die functional modules in the FPGA bare die without a built-in NOC network can achieve efficient intercommunication by means of the silicon connection layer interconnection framework, reducing the processing difficulty on the basis of improving the data transmission bandwidth and performance inside the FPGA device.

Abstract: The invention discloses a rice temperature sensitive male sterile gene mutant tms18 and its uses. During the study of TMS18 gene, the inventors found that the changing of fertility was related to the structural integrity of the second layer of pollen outer wall. The inventors accidentally found the thermo sensitive male sterile mutant tms18. The fertility of the mutant was affected by different temperatures and can be restored under low temperature treatment. More importantly, the fertility sensitive period of the mutant was different from that of other thermo sensitive male sterile genes. This unique feature of the gene can provide a new theoretical basis and apply value for two-line hybrid rice breeding.

Abstract: The present disclosure discloses an FPGA device for implementing a network-on-chip transmission bandwidth expansion function, and relates to the technical field of FPGAs. When a predefined functional module with built-in hardcore IP nodes is integrated in an FPGA bare die, soft-core IP nodes are configured and formed by using logical resource modules in the FPGA bare die and are connected to the hardcore IP nodes to form an NOC network structure, so as to increase nodes and expand the transmission bandwidth of the predefined functional module. On the other hand, the soft-core IP nodes can be additionally connected to input and output signals in the predefined functional module and also can expand the transmission bandwidth of the predefined functional module.