Abstract: An immersion cooling system is provided. It includes a pressure seal tank, an electronic module, a blower, and a distributor plate. The pressure seal tank contains a cooling liquid, and a gas outlet is disposed on the top or a sidewall of the pressure seal tank, a gas inlet is disposed on the bottom of the pressure seal tank. The gas outlet is higher than the liquid level of the cooling liquid. The electronic module is disposed in the pressure seal tank and immersed in the cooling liquid. The blower is communicated with the pressure seal tank and configured to extract the gas from the gas outlet and inject the gas into the pressure seal tank via the gas inlet. The distributor plate is disposed in the pressure seal tank and located between the electronic module and the gas inlet.

Abstract: A device for detecting soil nutrients on site, including an extracting grid, an on-site real-time detection assembly and a transfer assembly for transferring a soil extract from the extracting grid to the on-site real-time detection assembly. A soil nutrient detection method using the device and a microfluidic chip are also provided. The microfluidic chip includes a cover plate and a base plate. The base plate includes a soil extract feeding groove, a quantitative feeding groove, a reagent storage groove, and a serpentine groove.

Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.

Abstract: A semiconductor chip includes a physical layer and a processing circuit. The physical layer includes an input/output circuit, at least one sequence checking circuit and at least one signal transmission path, wherein the at least one sequence checking circuit is configured to generate at least one test result signal according to a clock signal transmitted through the input/output circuit and at least one test data signal transmitted through the at least one signal transmission path. The processing circuit is electrically coupled to the physical layer and is configured to determine an operation status of the at least one signal transmission path according to a voltage level of the at least one test result signal.

Abstract: A light-emitting diode (LED) includes a semiconductor structure, a transparent conducting layer, a first electrode, and a second electrode. The semiconductor structure has a lower surface and an upper surface, and includes a first semiconductor layer, an active layer, and a second semiconductor layer that are sequentially stacked in a laminating direction from the lower surface to the upper surface. The transparent conducting layer is located on the second semiconductor layer. The first electrode is located on the first semiconductor layer. The second electrode is located on the transparent conducting layer. When viewing the semiconductor structure and the transparent conducting layer from above the LED. The semiconductor structure has a shortest side with a length of X ?m.

Abstract: A method includes providing a fin extending from a substrate, the fin including a plurality of semiconductor channel layers, and where a gate is disposed over the fin. A first spacer layer is deposited over the gate and over the fin in a source/drain region. The first spacer layer has a first etch rate. A second spacer layer is deposited over the first spacer layer. The second spacer layer has a second etch rate less than the first etch rate. The plurality of semiconductor channel layers are removed from the source/drain region to form a trench having a funnel shape. After forming the trench, inner spacers are formed along a sidewall surface of the trench. In various embodiments, lateral sidewall surfaces of each semiconductor channel layer of the plurality of semiconductor channel layers is substantially free of an inner spacer material.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a first channel member suspended over a substrate and a second channel member suspended over the first channel member and spaced apart from the first channel member along a first direction. The semiconductor structure also includes a gate structure wrapping around the first channel member and the second channel member and a dielectric structure encircled by the first channel member, the second channel member, the gate structure, and the source/drain structure. In addition, the dielectric structure includes a porous material or an air gap. The semiconductor structure also includes a first epitaxial layer attached to the first channel member, and the first epitaxial layer has a first extending portion protruding from a bottom surface of the first channel member along the first direction and extending into the dielectric structure.

Abstract: A lens assembly includes a first lens group, a second lens group, a third lens group, a fourth lens group, a fifth lens group, a sixth lens group, and a first reflective element. The first and third lens groups are with negative refractive power. The second and fourth lens groups are with positive refractive power. The fifth and sixth lens groups are with refractive power. The first, second, third, fourth, fifth, and sixth lens groups are arranged in order from a first side to a second side along an axis. The first reflective element includes a first reflective surface. A light from the first side sequentially passes through the first, second, third, fourth, fifth, and sixth lens groups to the second side. The first reflective element is disposed between the first lens group and the sixth lens group.

Abstract: The present disclosure relates to methods of manufacturing at least a portion of a magnetic layer of a magnetic recording disk. The methods include forming a plurality of sacrificial, discrete structures via imprint lithography. The sacrificial, discrete structures are used to form a plurality of three-dimensional segregant structures in a magnetic layer of the magnetic recording disk. The present disclosure also relates to corresponding magnetic recording disks.

Abstract: Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a vertical stack of channel members disposed over a substrate, a gate structure wrapping around each channel member of the vertical stack of channel members, a source/drain feature coupled to the vertical stack of channel members and adjacent the gate structure; and a dielectric feature disposed between the source/drain feature and the substrate, in a cross-sectional view, the dielectric feature includes a V-shape sidewall surface.

Abstract: In one implementation, a method is performed for generating metadata estimations based on metadata subdivisions. The method includes: obtaining an input image; obtaining metadata associated with the input image; subdividing the metadata into a plurality of metadata subdivisions; determining a viewport relative to the input image based on at least one of head pose information and eye tracking information; generating one or more metadata estimations by performing an estimation algorithm on at least a portion of the plurality of metadata subdivisions based on the viewport; and generating an output image by performing an image processing algorithm on the input image based on the one or more metadata estimations.

Abstract: Some embodiments relate to an integrated circuit including one or more memory cells arranged over a semiconductor substrate between an upper metal interconnect layer and a lower metal interconnect layer. A memory cell includes a bottom electrode disposed over the lower metal interconnect layer, a data storage or dielectric layer disposed over the bottom electrode, and a top electrode disposed over the data storage or dielectric layer. An upper surface of the top electrode is in direct contact with the upper metal interconnect layer without a via or contact coupling the upper surface of the top electrode to the upper metal interconnect layer. Sidewall spacers are arranged along sidewalls of the top electrode, and have bottom surfaces that rest on an upper surface of the data storage or dielectric layer.

Abstract: A method for tuning a threshold voltage of a transistor is disclosed. A channel layer is formed over a substrate. An interfacial layer is formed over and surrounds the channel layer. A gate dielectric layer is formed over and surrounds the interfacial layer. A dipole layer is formed over and wraps around the gate dielectric layer by performing a cyclic deposition etch process, and the dipole layer includes dipole metal elements and has a substantially uniform thickness. A thermal drive-in process is performed to drive the dipole metal elements in the dipole layer into the gate dielectric layer to form an interfacial dipole surface, and then the dipole layer is removed.

Abstract: An underneath large-capacity single-gas-pump foam generating device includes a liquid replenishment mechanism and a foam generating mechanism. The liquid replenishment mechanism includes a liquid replenishment groove and a liquid replenishment bottle. The liquid replenishment bottle has a bottle opening sleeved in the liquid replenishment groove. The foam generating mechanism includes a gas supply pump unit, a gas mixing groove cavity, a gas-liquid mixing structure, a gas inlet and a vent valve structure. A lower portion of the gas mixing groove cavity is communicated with a lower portion of the liquid replenishment groove, a liquid replenishment one-way valve is arranged between the gas mixing groove cavity and the liquid replenishment groove. The gas-liquid mixing structure is provided with a liquid outlet channel, a gas outlet channel and a mixing channel, an inlet end of the liquid outlet channel extends downwardly into a bottom portion of the gas mixing groove cavity.

Abstract: A display may have an array of pixels. Display driver circuitry may supply data and control signals to the pixels. Each pixel may have seven transistors, a capacitor, and a light-emitting diode such as an organic light-emitting diode. The seven transistors may receive control signals using horizontal control lines. Each pixel may have first and second emission enable transistors that are coupled in series with a drive transistor and the light-emitting diode of that pixel. The first and second emission enable transistors may be coupled to a common control line or may be separately controlled so that on-bias stress can be effectively applied to the drive transistor. The display driver circuitry may have gate driver circuits that provide different gate line signals to different rows of pixels within the display. Different rows may also have different gate driver strengths and different supplemental gate line loading structures.

Abstract: A continuous sample introduction method is provided. The method includes controlling a current sample holder advancing mechanism to perform an advancing operation according to a sample introduction trigger signal, so that the current sample holder advancing mechanism moves in a direction from an initial position to a limiting position, and during the movement, a pushing portion of the current sample holder advancing mechanism is capable of abutting against a side wall of a sample holder in a current sample loading device; controlling the current sample holder advancing mechanism to perform a returning operation when the current sample holder advancing mechanism moves to the limiting position, and during the movement, the pushing portion is capable of avoiding contacting with the sample holder; and the current sample holder advancing mechanism automatically repeats the advancing operation and the returning operation when the current sample holder advancing mechanism moves to the initial position.

Abstract: An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is on a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is on a backside of the source epitaxial structure and a backside of the drain epitaxial structure and has an air gap therein. The backside via extends through the backside dielectric layer to a first one of the source epitaxial structure and the drain epitaxial structure.

Abstract: An optical fiber transmission device includes a substrate, a photonic integrated circuit, and an optical fiber assembly. The photonic integrated circuit is disposed on an area of the substrate. The substrate has a protruding structure at an interface with an edge of the photonic integrated circuit. The optical fiber assembly includes an optical fiber and a ferrule that sleeves the optical fiber. The protruding structure of the substrate is configured to abut against the ferrule to limit the position of the optical fiber assembly in a vertical direction of the substrate, such that the protruding structure is a stopper for the optical fiber assembly in the vertical direction.

Abstract: An optical fiber network device includes a fiber and a photonic integrated circuit. Fiber receives a first optical signal and transmits a second optical signal. A first wavelength of first optical signal is different from a second wavelength of second optical signal. Photonic integrated circuit includes a laser chip, a photodetector, a wavelength division multiplexing coupler, a first optical modulation element and a second optical modulation element. Laser chip is disposed on photonic integrated circuit, and is configured to generate first optical signal. Photodetector detects second optical signal. Wavelength division multiplexing coupler is configured to couple first optical signal to fiber, and receives second optical signal. First optical modulation element is coupled to wavelength division multiplexing coupler and laser chip, and is configured to modulate first optical signal.

Abstract: An image encoding/decoding method is provided. An image decoding method of the present invention may comprise deriving an intra-prediction mode of a current luma block, deriving an intra-prediction mode of a current chroma block based on the intra-prediction mode of the current luma block, generating a prediction block of the current chroma block based on the intra-prediction mode of the current chroma block, and the deriving of an intra-prediction mode of a current chroma block may comprise determining whether or not CCLM (Cross-Component Linear Mode) can be performed for the current chroma block.