Patents by Inventor Yang Chao

Yang Chao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12567973
    Abstract: The disclosure provides a Galois hash authentication-based circuit. An additional authentication data calculation circuit receives the first data block in the data stream and performs calculation according to the first data block, and shifts the calculation result to the left to generate a first output. A ciphertext calculation circuit includes k first calculation units, used to receive in parallel the second data blocks in the data stream in each round of calculation of the ciphertext calculation circuit, and perform parallel calculation on each data block received to generate a second output. The bubble processing circuit receives the first quantity of the third data blocks after the last round of calculation of the ciphertext calculation circuit and performs calculation to generate a third output. A message authentication code is calculated according to the first output, the second output, and the third output.
    Type: Grant
    Filed: September 23, 2024
    Date of Patent: March 3, 2026
    Assignee: Montage Electronics (Shanghai) Co., Ltd.
    Inventors: Jun Yang, Yang Chao, Men Long
  • Patent number: 12524237
    Abstract: A data padding method comprises: determining a length of a space occupied by remaining data in the register; comparing the length of the space occupied; performing, when the length of the space occupied by the remaining data is less than the length of the unit input data, following operations: receiving a unit input data and storing it continuously with the remaining data in the register; determining a length of a unit output data to be output; intercepting a portion of data with a length of N words from data formed by padding the remaining data buffered in the register and the unit input data and starting from an address space of a lowest bit of the register, as the unit output data and outputting it; and shifting the data remaining in the register as a whole to an address space in the register starting from the lowest bit.
    Type: Grant
    Filed: April 12, 2024
    Date of Patent: January 13, 2026
    Assignee: MONTAGE ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Yang Chao, Men Long, Xudong Xu, Jun Yang
  • Patent number: 12493516
    Abstract: A data security method and data security system configured to applied to a memory controller are provided. The data security method comprises: receiving a data writing request, wherein the data writing request comprises data to be written to a storage module and a storage address of the data; acquiring verification information of the data; and writing the data into the storage address, and writing the verification information into a redundant ECC bit corresponding to the data. The data security method and data security system according to the present disclosure can achieve the secure storage and reading of the data without extra space overhead, while maintaining high bandwidth and throughput.
    Type: Grant
    Filed: September 4, 2023
    Date of Patent: December 9, 2025
    Assignee: Montage Electronics (Shanghai) Co., Ltd.
    Inventors: Yang Chao, Zhaohui Du, Men Long, Xiaoyan Li, Dajiang Zhong
  • Patent number: 12341539
    Abstract: A data compression method includes: storing data to be written into a first address and a second address into a data buffer in response to a data write request to the first address and the second address of a memory module from a host; according to a relationship between the first address and the second address, selecting a compression scheme from pre-configured compression schemes, and attempting to compress the data to be written into the first address and the second address into compressed data that can be stored into either the first address or the second address by using a pre-defined compression method, if the attempt to compress successes, storing the compressed data into the first address or the second address of the memory module, and identifying the compressed data by using redundant ECC bits to form first identification information.
    Type: Grant
    Filed: July 20, 2023
    Date of Patent: June 24, 2025
    Assignee: MONTAGE TECHNOLOGY CO., LTD.
    Inventors: Xiaoyan Li, Zhaohui Du, Men Long, Yang Chao, Dajiang Zhong
  • Publication number: 20250106037
    Abstract: The disclosure provides a Galois hash authentication-based circuit. An additional authentication data calculation circuit receives the first data block in the data stream and performs calculation according to the first data block, and shifts the calculation result to the left to generate a first output. A ciphertext calculation circuit includes k first calculation units, used to receive in parallel the second data blocks in the data stream in each round of calculation of the ciphertext calculation circuit, and perform parallel calculation on each data block received to generate a second output. The bubble processing circuit receives the first quantity of the third data blocks after the last round of calculation of the ciphertext calculation circuit and performs calculation to generate a third output. A message authentication code is calculated according to the first output, the second output, and the third output.
    Type: Application
    Filed: September 23, 2024
    Publication date: March 27, 2025
    Applicant: Montage Electronics (Shanghai) Co., Ltd.
    Inventors: Jun Yang, Yang Chao, Men Long
  • Publication number: 20240378057
    Abstract: A data padding method comprises: determining a length of a space occupied by remaining data in the register; comparing the length of the space occupied; performing, when the length of the space occupied by the remaining data is less than the length of the unit input data, following operations: receiving a unit input data and storing it continuously with the remaining data in the register; determining a length of a unit output data to be output; intercepting a portion of data with a length of N words from data formed by padding the remaining data buffered in the register and the unit input data and starting from an address space of a lowest bit of the register, as the unit output data and outputting it; and shifting the data remaining in the register as a whole to an address space in the register starting from the lowest bit.
    Type: Application
    Filed: April 12, 2024
    Publication date: November 14, 2024
    Inventors: Yang CHAO, Men LONG, Xudong XU, Jun YANG
  • Publication number: 20240111690
    Abstract: This application relates to the field of memory technology, in particular to a method and a system for remapping a row address on a multichannel DIMM. The method is applied to a memory controller, comprising: receiving a first read/write access address and extracting a first channel row address from the first read/write access address; encrypting and mapping the first channel row address through a key-based mapping method to obtain a second channel row address that corresponds to the first channel row address within a predetermined address range; forming a second read/write access address based on the second channel row address and unextracted address information in the first read/write access address, and performing read/write access to the DIMM based on the second read/write access address. The present application can alleviate side channel attack without causing degradation of read/write performance.
    Type: Application
    Filed: September 27, 2023
    Publication date: April 4, 2024
    Applicant: MONTAGE TECHNOLOGY CO., LTD.
    Inventors: Xiaoyan LI, Zhaohui DU, Men LONG, Yang CHAO, Dajiang ZHONG, Zhixin TIAN
  • Publication number: 20240078151
    Abstract: A data security method and data security system configured to applied to a memory controller are provided. The data security method comprises: receiving a data writing request, wherein the data writing request comprises data to be written to a storage module and a storage address of the data; acquiring verification information of the data; and writing the data into the storage address, and writing the verification information into a redundant ECC bit corresponding to the data. The data security method and data security system according to the present disclosure can achieve the secure storage and reading of the data without extra space overhead, while maintaining high bandwidth and throughput.
    Type: Application
    Filed: September 4, 2023
    Publication date: March 7, 2024
    Applicant: Montage Electronics (Shanghai) Co., Ltd.
    Inventors: Yang CHAO, Zhaohui DU, Men LONG, Xiaoyan LI, Dajiang ZHONG
  • Publication number: 20240030937
    Abstract: A data compression method includes: storing data to be written into a first address and a second address into a data buffer in response to a data write request to the first address and the second address of a memory module from a host; according to a relationship between the first address and the second address, selecting a compression scheme from pre-configured compression schemes, and attempting to compress the data to be written into the first address and the second address into compressed data that can be stored into either the first address or the second address by using a pre-defined compression method, if the attempt to compress successes, storing the compressed data into the first address or the second address of the memory module, and identifying the compressed data by using redundant ECC bits to form first identification information.
    Type: Application
    Filed: July 20, 2023
    Publication date: January 25, 2024
    Applicant: MONTAGE TECHNOLOGY CO., LTD.
    Inventors: Xiaoyan LI, Zhaohui DU, Men LONG, Yang CHAO, Dajiang ZHONG
  • Patent number: 11525966
    Abstract: An optical coupling apparatus is disclosed, including: a monochromatic light source configured to emit monochromatic light; a monochromatic light photodetector configured to receive the monochromatic light; and a monochromatic light transmission medium, wherein at least a portion of the monochromatic light transmission medium is disposed between the monochromatic light source and the monochromatic light photodetector, and the monochromatic light is transmitted to the monochromatic light photodetector via the monochromatic light transmission medium, wherein a wavelength of the monochromatic light is shorter than a wavelength of infrared light. Embodiments of the present disclosure provide an optical coupling apparatus with a higher upper limit of operating frequency, which may better meet user requirements.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: December 13, 2022
    Assignee: NINGBO QUNXIN MICRO-ELECTRONICS CO., LTD
    Inventor: Yang Chao
  • Publication number: 20210405305
    Abstract: An optical coupling apparatus is disclosed, including: a monochromatic light source configured to emit monochromatic light; a monochromatic light photodetector configured to receive the monochromatic light; and a monochromatic light transmission medium, wherein at least a portion of the monochromatic light transmission medium is disposed between the monochromatic light source and the monochromatic light photodetector, and the monochromatic light is transmitted to the monochromatic light photodetector via the monochromatic light transmission medium, wherein a wavelength of the monochromatic light is shorter than a wavelength of infrared light. Embodiments of the present disclosure provide an optical coupling apparatus with a higher upper limit of operating frequency, which may better meet user requirements.
    Type: Application
    Filed: October 27, 2020
    Publication date: December 30, 2021
    Applicant: NINGBO QUNXIN MICRO-ELECTRONICS CO., LTD
    Inventor: Yang CHAO
  • Publication number: 20200350169
    Abstract: A wafer bonding method comprises providing a first wafer and a second wafer, the first wafer having a first metal layer and a first insulating layer at a first surface thereof, the second wafer having a second metal layer and a second insulating layer at a first surface thereof, the first metal layer and the second metal layer comprising a same metal material; pretreating one or both of the first wafer and the second wafer, so that whiskers of the metal material are formed at a surface or surfaces of the one or both of the first metal layer and the second metal layer; and bonding the first metal layer and the second metal layer in a manner that the first metal layer and the second metal layer face each other, to bond the first wafer and the second wafer.
    Type: Application
    Filed: September 6, 2019
    Publication date: November 5, 2020
    Applicant: HUAIAN IMAGING DEVICE MANUFACTURER CORPORATION
    Inventors: Xian Zhou, Yang Chao, Xiaolu Huang
  • Publication number: 20200301954
    Abstract: This application discloses a reply information obtaining method and apparatus. The method includes: determining a target keyword corresponding to target question information according to the target question information obtained by a client; determining, according to the target keyword, a target information topic to which the target question information belongs in a plurality of information topics; and obtaining target reply information corresponding to the target question information from a target information group in a plurality of information groups, the target information group including a plurality of pairs of question information and reply information that correspond to each other, and the question information included in the target information group belonging to the target information topic. This application resolves a technical problem of relatively low efficiency of obtaining the reply information in the related art.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Inventors: Yang CHAO, Yao LV, Dong LI, Guangyuan SUN, Ran WEI, Tao ZHENG
  • Patent number: 10600667
    Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: March 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Yang Chao, Keith E. Ypma, Steve J. Strauch
  • Publication number: 20200016424
    Abstract: An electromagnetic field generating apparatus for treating pathological cells, in particular with tumor suppression function. The ratio of static magnetic field to alternating magnetic field is in the range of 0.5-2.5, and the total intensity is in the range up to 100 mT. It provides non-invasive low toxicity and side effects, significantly inhibiting a plurality of tumors, influencing the intracellular superoxide radical content, and promoting cell autophagy. The mechanism of action of the magnetic field is on the electron spin energy levels and consequently on the free radicals concentration. Additional magnetic field having frequency up to 100 MHz and intensity down to microTesla range can be also used to improve the antitumor efficacy in combination with the static as well as the extremely low frequency electromagnetic field (1-300 Hz) influencing the spin hyperfine resonance. A combination method is also provided of a power-frequency electromagnetic field generating device and a platinum-based medicine.
    Type: Application
    Filed: February 7, 2018
    Publication date: January 16, 2020
    Applicants: ZHEJIANG UNIVERSITY
    Inventors: Santi TOFANI, Chen XI, Yuan LINQING, Shi KEXIN, Yang CHAO, Bian SUCHEN, Wang JINHU, Zhu KUN, Yang MIN, Gu WEIZHONG, Shang SHIQIANG, Li HUAMEI, Shen ZHENG, Wang CAN
  • Publication number: 20190279892
    Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.
    Type: Application
    Filed: May 23, 2019
    Publication date: September 12, 2019
    Inventors: Yang Chao, Keith E. Ypma, Steve J. Strauch
  • Patent number: 10347519
    Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the water based on the comparison.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: July 9, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Yang Chao, Keith E. Ypma, Steve J. Strauch
  • Publication number: 20190148202
    Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.
    Type: Application
    Filed: January 15, 2019
    Publication date: May 16, 2019
    Inventors: Yang Chao, Keith E. Ypma, Steve J. Strauch
  • Patent number: 10242901
    Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: March 26, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Yang Chao, Keith E. Ypma, Steve J. Strauch
  • Publication number: 20180330976
    Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.
    Type: Application
    Filed: July 26, 2018
    Publication date: November 15, 2018
    Inventors: Yang Chao, Keith E. Ypma, Steve J. Strauch