Abstract: A semiconductor structure includes: a first semiconductor die or wafer including a first bonding crack detection structure portion including discrete bonding crack detection structure portions that are electrically isolated, and a second semiconductor die or wafer bonded to the first semiconductor die, the second semiconductor die or wafer including a second bonding crack detection structure portion including discrete bonding crack detection structure portions that are electrically isolated, wherein the first bonding crack detection structure portion and the second bonding crack detection structure portion are bonded together to form a bonding crack detection structure.

Abstract: A method of testing a semiconductor package includes: attaching a charge measurement unit to a carrier substrate; forming a first metallization layer over the charge measurement unit, wherein the forming of the first metallization layer induces first charges to accumulate on the charge measurement unit; performing a first test against the charge measurement unit to determine whether breakdown occurs in the charge measurement unit; and in response to determining that no breakdown occurs in the charge measurement unit, forming a second metallization layer over the first metallization layer.

Abstract: A semiconductor includes a first substrate having a device region and a ring region surrounding the device region, a first interconnect structure over the first substrate, the first interconnect structure including a first via tower and a second via tower, a first bonding layer over the first interconnect structure and including a first metal bonding feature, a second bonding layer over the first bonding layer and including a second metal bonding feature in contact with the first metal bonding feature, and a second interconnect structure over the second bonding layer and including a third via tower extending through the second interconnect structure and disposed directly over the ring region. The first via tower is electrically coupled to the second via tower by a first metal line. The first via tower is electrically coupled to the third via tower by the first metal bonding feature and the second metal bonding feature.

Abstract: A method includes forming a solder layer on a surface of one or more chips. A lid is positioned over the solder layer on each of the one or more chips. Heat and pressure are applied to melt the solder layer and attach each lid to a corresponding solder layer. The solder layer has a thermal conductivity of ?50 W/mK.

Abstract: A method of testing a semiconductor package includes: forming a charge measurement unit over a carrier substrate; forming a first dielectric layer over the charge measurement unit; forming a first metallization layer over the dielectric layer, wherein the forming of the first metallization layer induces first charges to accumulate on the charge measurement unit; performing a first test against the charge measurement unit to determine whether breakdown occurs in the charge measurement unit; and in response to determining that no breakdown occurs in the charge measurement unit, forming a second dielectric layer over the first metallization layer.

Abstract: An integrated circuit (IC) package includes a first integrated circuit (IC) device. An interconnection structure is disposed over the first IC device in a cross-sectional side view. The interconnection structure includes a plurality of interconnection components. A cavity is disposed in the interconnection structure in the cross-sectional side view. A second IC device is disposed at least partially within the cavity in the cross-sectional side view. The second IC device is electrically coupled to the first IC device through at least a subset of the interconnection components of the interconnection structure. A non-metallic material partially fills the cavity. The second IC device is at least partially surrounded by the non-metallic material in the cross-sectional side view and in a top view.

Abstract: A semiconductor structure includes an interconnect structure, a passivation structure, a first capacitor, and a contact feature. The interconnect structure is disposed over a semiconductor substrate. The passivation structure is disposed over the interconnect structure. The first capacitor is disposed within the passivation structure. The contact feature is disposed over the passivation structure, wherein the first capacitor is proximal to a corner of the contact feature. A method of manufacturing the semiconductor structure is also provided.

Abstract: A semiconductor structure includes a first die; a molding surrounding the first die; a redistribution layer (RDL) disposed under the first die and the molding, and including a plurality of first conductive pads and a dielectric layer surrounding the plurality of first conductive pads; a second die disposed under the RDL, and including a plurality of first die pads over the second die; and a plurality of first conductive bumps disposed between the RDL and the second die, wherein each of the plurality of first conductive bumps is electrically coupled with corresponding one of the plurality of first die pads and corresponding one of the plurality of first conductive pads, the plurality of first die pads are respectively arranged at corners of the second die, and the plurality of first conductive bumps are electrically connected in series.

Abstract: A method includes forming a solder layer on a surface of one or more chips. A lid is positioned over the solder layer on each of the one or more chips. Heat and pressure are applied to melt the solder layer and attach each lid to a corresponding solder layer. The solder layer has a thermal conductivity of ?50 W/mK.

Abstract: A semiconductor package structure includes a semiconductor die encapsulated in a molding compound, a redistribution structure over the semiconductor die and the molding compound, a surface device over and electrically connected to the redistribution structure, a first connector over and electrically connected to the redistribution structure, a second connector between the surface device and the redistribution structure, a trench in the redistribution structure and laterally surrounding the surface device in a top view of the semiconductor package structure, and an underfill. The second connector electrically connects the surface device to the redistribution structure. The underfill surrounds the second connector. The underfill include a first portion and a second portion. The first portion of the underfill is located between the surface device and the redistribution structure and laterally surrounding the second connector, and the second portion of the underfill is disposed in the trench.

Abstract: A semiconductor package includes a semiconductor chip disposed over a first main surface of a first substrate, a package lid disposed over the semiconductor chip, and spacers extending from the package lid through corresponding holes in the first substrate. The spacers enter the holes at a first main surface of the first substrate and extend beyond an opposing second main surface of the first substrate.

Abstract: A micro electro mechanical system (MEMS) includes a circuit substrate, a first MEMS structure disposed over the circuit substrate, and a second MEMS structure disposed over the first MEMS structure.

Abstract: The present disclosure provides a semiconductor structure including a vertical inductor. The semiconductor structure includes a first semiconductor substrate, a first conductive layer, a first magnetic layer, and a second magnetic layer. The first semiconductor substrate has a top surface, and the first conductive layer is vertically inserted into the first semiconductor substrate from the top surface of the first semiconductor substrate. The first magnetic layer is disposed in the first semiconductor substrate and surrounds the first conductive layer. The second magnetic layer is disposed over the first conductive layer and the first magnetic layer.

Abstract: A semiconductor package includes a semiconductor chip disposed over a first main surface of a first substrate, a package lid disposed over the semiconductor chip, and spacers extending from the package lid through corresponding holes in the first substrate. The spacers enter the holes at a first main surface of the first substrate and extend beyond an opposing second main surface of the first substrate.

Abstract: A micro electro mechanical system (MEMS) includes a circuit substrate, a first MEMS structure disposed over the circuit substrate, and a second MEMS structure disposed over the first MEMS structure.

Abstract: An inductive device includes an insulating layer, a lower magnetic layer, and an upper magnetic layer that are formed such that the insulating layer does not separate the lower magnetic layer and the upper magnetic layer at the outer edges or wings of the inductive device. The lower magnetic layer and the upper magnetic layer form a continuous magnetic layer around the insulating layer and the conductors of the inductive device. Magnetic leakage paths are provided by forming openings through the upper magnetic layer. The openings may be formed through the upper magnetic layer by semiconductor processes that have relatively higher precision and accuracy compared to semiconductor processes for forming the insulating layer such as spin coating. This reduces magnetic leakage path variation within the inductive device and from inductive device to inductive device.

Abstract: A semiconductor device includes a first circuit area disposed over a substrate and enclosed by a first seal ring structure, a second circuit area disposed over the substrate and enclosed by a second seal ring structure, an internal scribe line disposed between the first circuit area and the second circuit area, and connecting seal structures connecting the first seal ring structure and the second seal ring structures such that a part of the first seal ring structure, a part of the second seal ring structure and the connecting seal structures enclose the internal scribe line.

Abstract: A semiconductor structure includes a molding compound having a first surface and a second surface opposite to the first surface, a passive device component disposed in the molding compound, a via penetrating the molding compound from the first surface to the second surface, a first connection structure disposed over the first surface of the molding compound and electrically coupled to the passive device component, and a second connection structure disposed over the second surface of the molding compound. The first connection structure and the second connection structure are electrically coupled to each other by the via.

Abstract: A semiconductor structure includes a recess extending into a substrate and an inductor device including a first isolation layer, a first magnetic layer over the first isolation layer, a second isolation layer over the first magnetic layer, and a conductive element surrounded by the second isolation layer, wherein at least a portion of the inductor device is disposed within the recess. A method of manufacturing a semiconductor structure includes disposing a first isolation layer on a surface of a substrate and extending into a recess formed on the surface; disposing a first magnetic layer over the first isolation layer; disposing a second isolation layer over the first magnetic layer to form a trench; disposing a conductive element in the trench; disposing a third isolation layer over the first magnetic layer, the conductive element and the second isolation layer; and disposing a second magnetic layer over the third isolation layer.

Abstract: A method for detecting defects in a semiconductor device including singulating a die having a substrate including a circuit region and an outer border, a plurality of detecting devices disposed over the substrate and located between the circuit region and the outer border, a first probe pad and a second probe pad electrically connected to two ends of each detecting device, and a seal ring located between the outer border of the die and the detecting devices. The method further includes probing the first probe pad and the second probe pad to determine a connection status of the detecting device, and recognizing a defect when the connection status of the detecting device indicates an open circuit.