Patents by Inventor Yang-Chieh Lin

Yang-Chieh Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10415627
    Abstract: The present invention mainly aims to rebuilt the structures of a hook body, valve and control handle and the link relationship thereof. The outer surface of two shrouds of the control handle are respectively stamped with a depression adapted project a similar limit block out of the inner surface of each shroud, the limit block having upper, lower blocking surfaces opposite to each other vertically, and the upper, lower blocking surfaces are further controlled to be perpendicular to the shroud, thereby allowing them to transfer stably the stress between the hook body and valve when withstanding the stress due to the inadvertent opening of the valve so that the valve and limit blocks are not deformed easily, have a longer use and enhance the overall use safety greatly.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: September 17, 2019
    Assignee: AKILA TECH CO., LTD.
    Inventors: Yang-Tsung Chen, Yi-Ching Lin, Kai-Chieh Yang
  • Patent number: 9455039
    Abstract: A charge pump system includes a plurality of pump units, a control circuit, and a detection circuit. The plurality of pump units are used for generating a pump output voltage. The control circuit is coupled to the plurality of pump units and is used for controlling each pump unit of the plurality of pump units. The detection circuit is coupled to the control circuit and the plurality of pump units and is used for detecting the pump output voltage. When the pump output voltage is greater than a predetermined value, the detection circuit generates and latches a control signal to enable the control circuit. After the control circuit is enabled, when the pump output voltage is detected to be smaller than the predetermined value, the detection circuit generates a first pump enable signal to the control circuit for enabling a first pump unit of the plurality of pump units.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: September 27, 2016
    Assignee: eMemory Technology Inc.
    Inventor: Yang-Chieh Lin
  • Publication number: 20160141040
    Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal
    Type: Application
    Filed: November 5, 2015
    Publication date: May 19, 2016
    Inventors: Chung-Zen CHEN, Yang-Chieh LIN, Chung-Shan KUO
  • Publication number: 20160105100
    Abstract: A charge pump system includes a plurality of pump units, a control circuit, and a detection circuit. The plurality of pump units are used for generating a pump output voltage. The control circuit is coupled to the plurality of pump units and is used for controlling each pump unit of the plurality of pump units. The detection circuit is coupled to the control circuit and the plurality of pump units and is used for detecting the pump output voltage. When the pump output voltage is greater than a predetermined value, the detection circuit generates and latches a control signal to enable the control circuit. After the control circuit is enabled, when the pump output voltage is detected to be smaller than the predetermined value, the detection circuit generates a first pump enable signal to the control circuit for enabling a first pump unit of the plurality of pump units.
    Type: Application
    Filed: October 2, 2015
    Publication date: April 14, 2016
    Inventor: Yang-Chieh Lin
  • Patent number: 9214233
    Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: December 15, 2015
    Assignee: Conversant Intellectual Property Management Inc.
    Inventors: Chung-Zen Chen, Yang-Chieh Lin, Chung-Shan Kuo
  • Publication number: 20130250695
    Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.
    Type: Application
    Filed: May 16, 2013
    Publication date: September 26, 2013
    Applicant: Mosaid Technologies Incorporated
    Inventors: Chung-Zen Chen, Yang-Chieh Lin, Chung-Shan Kuo
  • Patent number: 8456922
    Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: June 4, 2013
    Assignee: MOSAID Technologies Incorporated
    Inventors: Chung-Zen Chen, Yang-Chieh Lin, Chung-Shan Kuo
  • Publication number: 20120230119
    Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.
    Type: Application
    Filed: May 22, 2012
    Publication date: September 13, 2012
    Applicant: MOSAID Technologies Incorporated
    Inventors: Chung-Zen Chen, Yang-Chieh Lin, Chung-Shan Kuo
  • Patent number: 8189396
    Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: May 29, 2012
    Assignee: Mosaid Technologies Incorporated
    Inventors: Chung-Zen Chen, Yang-Chieh Lin, Chung-Shan Kuo
  • Patent number: 7443230
    Abstract: A charge pump circuit including a plurality of controlled charge pumps (CPs), a plurality of uncontrolled CPs, a plurality of control units, and an output unit is provided. Each controlled CP determines whether to provide charges to a node by a control signal, and each uncontrolled CP constantly provides charges to the node. The higher the node voltage at the node is, the more the controlled CPs not providing charge to the node are, so as to suppress the voltage of the node. In addition, the output unit regulates and outputs an output voltage according to the node voltage by the negative feedback.
    Type: Grant
    Filed: August 10, 2006
    Date of Patent: October 28, 2008
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventors: Chung-Zen Chen, Chung-Shan Kuo, Yang-Chieh Lin
  • Publication number: 20080144389
    Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.
    Type: Application
    Filed: December 14, 2006
    Publication date: June 19, 2008
    Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventors: Chung-Zen Chen, Yang-Chieh Lin, Chung-Shan Kuo
  • Patent number: 7382661
    Abstract: A program method for a flash memory semiconductor device includes the steps of providing a bit line voltage for programming a group of memory cells and detecting if the bit line voltage meets a selected target voltage. When the bit line voltage meets the selected target voltage, a program operation is performed on the group of memory cells. When the bit line voltage does not meet the selected target voltage, the programming operation is individually performed on at least a first subgroup of memory cells from the group and a second subgroup of memory cells from the group.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: June 3, 2008
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventor: Yang-Chieh Lin
  • Publication number: 20080036528
    Abstract: A charge pump circuit including a plurality of controlled charge pumps (CPs), a plurality of uncontrolled CPs, a plurality of control units, and an output unit is provided. Each controlled CP determines whether to provide charges to a node by a control signal, and each uncontrolled CP constantly provides charges to the node. The higher the node voltage at the node is, the more the controlled CPs not providing charge to the node are, so as to suppress the voltage of the node. In addition, the output unit regulates and outputs an output voltage according to the node voltage by the negative feedback.
    Type: Application
    Filed: August 10, 2006
    Publication date: February 14, 2008
    Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventors: Chung-Zen Chen, Chung-Shan Kuo, Yang-Chieh Lin
  • Patent number: 7324386
    Abstract: A method for erasing a flash memory group is provided, which comprises the following steps. (a) Apply a erase (ERS) pulse to a first subset of the group. (b) Perform one of a soft program verification (SPGMV) and a tight soft program verification (TSPGMV) on the first subset of the group. (c) Repeat steps (a) and (b) until a first predetermined condition is true. (d) Perform an erase verification (ERSV) on a second subset of the group. (e) Repeat steps (a) to (d) until a second predetermined condition is true. And (f) fix bit line leakage in a third subset of the group with a slow program (SLPGM) and apply an ERS pulse to the third subset.
    Type: Grant
    Filed: April 20, 2006
    Date of Patent: January 29, 2008
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventor: Yang-Chieh Lin
  • Publication number: 20070247922
    Abstract: A method for erasing a flash memory group is provided, which comprises the following steps. (a) Apply a erase (ERS) pulse to a first subset of the group. (b) Perform one of a soft program verification (SPGMV) and a tight soft program verification (TSPGMV) on the first subset of the group. (c) Repeat steps (a) and (b) until a first predetermined condition is true. (d) Perform an erase verification (ERSV) on a second subset of the group. (e) Repeat steps (a) to (d) until a second predetermined condition is true. And (f) fix bit line leakage in a third subset of the group with a slow program (SLPGM) and apply an ERS pulse to the third subset.
    Type: Application
    Filed: April 20, 2006
    Publication date: October 25, 2007
    Inventor: Yang-Chieh Lin
  • Patent number: 7132879
    Abstract: A boost circuit capable of boosting a reference voltage into an output voltage. The boost circuit includes a main transistor electrically connected to the output voltage, an auxiliary transistor electrically connected to the output voltage, a pre-charge circuit electrically connected to the main transistor and the auxiliary transistor for pre-charging the main transistor and the auxiliary transistor, and a voltage detector electrically connected to the auxiliary transistor and the reference voltage for controlling the auxiliary transistor according to the reference voltage.
    Type: Grant
    Filed: October 13, 2004
    Date of Patent: November 7, 2006
    Assignee: AMIC Technology Corporation
    Inventors: Yin-Chang Chen, Yang-Chieh Lin
  • Publication number: 20060038606
    Abstract: A boost circuit capable of boosting a reference voltage into an output voltage. The boost circuit includes a main transistor electrically connected to the output voltage, an auxiliary transistor electrically connected to the output voltage, a pre-charge circuit electrically connected to the main transistor and the auxiliary transistor for pre-charging the main transistor and the auxiliary transistor, and a voltage detector electrically connected to the auxiliary transistor and the reference voltage for controlling the auxiliary transistor according to the reference voltage.
    Type: Application
    Filed: October 13, 2004
    Publication date: February 23, 2006
    Inventors: Yin-Chang Chen, Yang-Chieh Lin