Patents by Inventor Yang-Chih Hsueh
Yang-Chih Hsueh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250149497Abstract: A bonding tool for bonding semiconductor dies to a semiconductor wafer is provided. The bonding tool includes a wafer chuck, an edge support, a hard plate, and a buffer layer. The wafer chuck carries the semiconductor wafer and the semiconductor dies placed on the semiconductor wafer. The edge support is disposed on the wafer chuck, the semiconductor wafer and the semiconductor dies are laterally surrounded by the edge support, and a top surface of the edge support substantially levels with surfaces of the semiconductor dies. The hard plate is movably disposed over the semiconductor dies, the edge support and the wafer chuck. The buffer layer is disposed on a bottom surface of the hard plate, and the buffer layer is in contact with the top surface of the edge support and the semiconductor dies when the hard plate moves towards the edge support.Type: ApplicationFiled: November 8, 2023Publication date: May 8, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Tsu Chung, Yung-Chi Lin, Yan-Zuo Tsai, Yang-Chih Hsueh
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Publication number: 20250070045Abstract: In a package device, wherein integrated circuit devices are bonded to a substrate, stress arising from mechanical strain, CTE mismatch, and the like can be alleviated or eliminated by incorporating stress buffering air gaps into a protective material, such as a gap fill oxide. The air gaps can be formed by tuning and changing deposition parameters during the deposition process and/or by tuning the size and placement of adjacent integrated circuit devices in the package, and/or by forming trenches in the protective material prior to the bonding process.Type: ApplicationFiled: January 3, 2024Publication date: February 27, 2025Inventors: Ming-Tsu Chung, Yung-Chi Lin, Yan-Zuo Tsai, Yang-Chih Hsueh
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Publication number: 20250062204Abstract: A package includes a first die over and bonded to a first side of a second die, where the second die includes a first substrate, a first interconnect structure over the first substrate, a seal ring disposed within the first interconnect structure, first dummy through substrate vias (TSVs) extending through edge regions of the first substrate of the second die and in physical contact with the seal ring, and functional TSVs extending through a central region of the first substrate of the second die.Type: ApplicationFiled: January 4, 2024Publication date: February 20, 2025Inventors: Yan-Zuo Tsai, Ming-Tsu Chung, Yang-Chih Hsueh, Yung-Chi Lin
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Publication number: 20250062136Abstract: A method includes bonding a device die onto a package component. The device die includes a semiconductor substrate, and a through-via extending into the semiconductor substrate. The method further includes depositing a dielectric liner lining sidewalls of the device die, depositing a dielectric layer on the dielectric liner, and planarizing the dielectric layer and the device die. Remaining portions of the dielectric liner and the dielectric layer form a gap-filling region, and a top end of the through-via is revealed. An implantation process is performed to introduce a stress modulation dopant into at least one of the dielectric liner and the dielectric layer. A redistribution line is formed over and electrically connecting to the through-via.Type: ApplicationFiled: November 20, 2023Publication date: February 20, 2025Inventors: Ming-Tsu Chung, Yung-Chi Lin, Yan-Zuo Tsai, Yang-Chih Hsueh, Ming-Shih Yeh
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Publication number: 20250062247Abstract: A method includes depositing a dielectric layer on a package component having a first warpage, and performing an implantation process to implant the dielectric layer with a stress modulation dopant. After the implantation process, the package component has a second warpage smaller than the first warpage.Type: ApplicationFiled: November 7, 2023Publication date: February 20, 2025Inventors: Yang-Chih Hsueh, Yan-Zuo Tsai, Ming-Tsu Chung, Yung-Chi Lin
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Publication number: 20240170320Abstract: A die bonding device is provided to pick up a die and place the die on a carrier. The die bonding device includes a pick-and-placer and a vacuum generator. The pick-and-placer includes an adsorption surface, a first channel and a second channel, and the first channel and the second channel are not connected to each other. The vacuum generator includes a first vacuum pump and a second vacuum pump, the first vacuum pump is connected to the first channel via a pipeline, the second vacuum pump is connected to the second channel via another pipeline, the first vacuum pump and the second vacuum pump make the pick-and-placer adsorb the die to the adsorption surface during a vacuum holding period, and the first vacuum pump and the second vacuum pump respectively make the pick-and-placer release the die to the carrier sequentially in a vacuum release period.Type: ApplicationFiled: January 19, 2023Publication date: May 23, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yan-Zuo TSAI, Yang-Chih HSUEH, Yung-Chi LIN
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Patent number: 11948920Abstract: Provided are a semiconductor device and a method for manufacturing the same, and a semiconductor package. The semiconductor device includes a die stack and a cap substrate. The die stack includes a first die, second dies stacked on the first die, and a third die stacked on the second dies. The first die includes first through semiconductor vias. Each of the second dies include second through semiconductor vias. The third die includes third through semiconductor vias. The cap substrate is disposed on the third die of the die stack. A sum of a thickness of the third die and a thickness of the cap substrate ranges from about 50 ?m to about 80 ?m.Type: GrantFiled: August 30, 2021Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-Chun Hsu, Yan-Zuo Tsai, Chia-Yin Chen, Yang-Chih Hsueh, Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou
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Publication number: 20230063851Abstract: Provided are a semiconductor device and a method for manufacturing the same, and a semiconductor package. The semiconductor device includes a die stack and a cap substrate. The die stack includes a first die, second dies stacked on the first die, and a third die stacked on the second dies. The first die includes first through semiconductor vias. Each of the second dies include second through semiconductor vias. The third die includes third through semiconductor vias. The cap substrate is disposed on the third die of the die stack. A sum of a thickness of the third die and a thickness of the cap substrate ranges from about 50 ?m to about 80 ?m.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-Chun Hsu, Yan-Zuo Tsai, Chia-Yin Chen, Yang-Chih Hsueh, Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou
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Patent number: 10867831Abstract: A method and apparatus for bonding semiconductor devices are disclosed. In an embodiment, the method may include attaching a first die to a flip head of a flip module, flipping the first die with the flip module, removing the first die from the flip module after flipping the first die, inspecting the flip head of the flip module for contamination after removing the first die, cleaning the flip head with an in situ cleaning module after inspecting the flip head, and attaching a second die to the flip head after cleaning the flip head.Type: GrantFiled: August 14, 2020Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yan-Zuo Tsai, Yang-Chih Hsueh, Chia-Yin Chen, Fu-Kang Tien, Ebin Liao, Wen-Chih Chiou
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Publication number: 20200373185Abstract: A method and apparatus for bonding semiconductor devices are disclosed. In an embodiment, the method may include attaching a first die to a flip head of a flip module, flipping the first die with the flip module, removing the first die from the flip module after flipping the first die, inspecting the flip head of the flip module for contamination after removing the first die, cleaning the flip head with an in situ cleaning module after inspecting the flip head, and attaching a second die to the flip head after cleaning the flip head.Type: ApplicationFiled: August 14, 2020Publication date: November 26, 2020Inventors: Yan-Zuo Tsai, Yang-Chih Hsueh, Chia-Yin Chen, Fu-Kang Tien, Ebin Liao, Wen-Chih Chiou
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Patent number: 10748803Abstract: A method and apparatus for bonding semiconductor devices are disclosed. In an embodiment, the method may include attaching a first die to a flip head of a flip module, flipping the first die with the flip module, removing the first die from the flip module after flipping the first die, inspecting the flip head of the flip module for contamination after removing the first die, cleaning the flip head with an in situ cleaning module after inspecting the flip head, and attaching a second die to the flip head after cleaning the flip head.Type: GrantFiled: April 22, 2019Date of Patent: August 18, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yan-Zuo Tsai, Yang-Chih Hsueh, Chia-Yin Chen, Fu-Kang Tien, Ebin Liao, Wen-Chih Chiou
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Publication number: 20190244851Abstract: A method and apparatus for bonding semiconductor devices are disclosed. In an embodiment, the method may include attaching a first die to a flip head of a flip module, flipping the first die with the flip module, removing the first die from the flip module after flipping the first die, inspecting the flip head of the flip module for contamination after removing the first die, cleaning the flip head with an in situ cleaning module after inspecting the flip head, and attaching a second die to the flip head after cleaning the flip head.Type: ApplicationFiled: April 22, 2019Publication date: August 8, 2019Inventors: Yan-Zuo Tsai, Yang-Chih Hsueh, Chia-Yin Chen, Fu-Kang Tien, Ebin Liao, Wen-Chih Chiou
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Patent number: 10269611Abstract: A method and apparatus for bonding semiconductor devices are disclosed. In an embodiment, the method may include attaching a first die to a flip head of a flip module, flipping the first die with the flip module, removing the first die from the flip module after flipping the first die, inspecting the flip head of the flip module for contamination after removing the first die, cleaning the flip head with an in situ cleaning module after inspecting the flip head, and attaching a second die to the flip head after cleaning the flip head.Type: GrantFiled: March 19, 2018Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yan-Zuo Tsai, Yang-Chih Hsueh, Chia-Yin Chen, Fu-Kang Tien, Ebin Liao, Wen-Chih Chiou
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Patent number: 10032698Abstract: An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad.Type: GrantFiled: June 5, 2017Date of Patent: July 24, 2018Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Hsiao Yun Lo, Yung-Chi Lin, Yang-Chih Hsueh, Tsang-Jiuh Wu, Wen-Chih Chiou
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Patent number: 9901917Abstract: The present invention provides methods and designs of enclosed-channel reactor system for manufacturing catalysts or supports. Both of the configuration designs force the gaseous precursors and purge gas flow through the channel surface of reactor. The precursors will transform to thin film or particle catalysts or supports under adequate reaction temperature, working pressure and gas concentration. The reactor body is either sealed or enclosed for isolation from atmosphere. Another method using super ALD cycles is also proposed to grow alloy catalysts or supports with controllable concentration. The catalysts prepared by the method and system in the present invention are noble metals, such as platinum, palladium, rhodium, ruthenium, iridium and osmium, or transition metals such as iron, silver, cobalt, nickel and tin, while supports are silicon oxide, aluminum oxide, zirconium oxide, cerium oxide or magnesium oxide, or refractory metals, which can be chromium, molybdenum, tungsten or tantalum.Type: GrantFiled: May 17, 2016Date of Patent: February 27, 2018Assignee: NATIONAL APPLIED RESEARCH LABORATORIESInventors: Chi-Chung Kei, Bo-Heng Liu, Chien-Pao Lin, Chien-Nan Hsiao, Yang-Chih Hsueh, Tsong-Pyng Perng
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Publication number: 20170271242Abstract: An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad.Type: ApplicationFiled: June 5, 2017Publication date: September 21, 2017Inventors: Hsiao Yun Lo, Yung-Chi Lin, Yang-Chih Hsueh, Tsang-Jiuh Wu, Wen-Chih Chiou
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Patent number: 9673132Abstract: An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad.Type: GrantFiled: October 9, 2014Date of Patent: June 6, 2017Assignee: Taiwan Semiconductor Manufacting Company, Ltd.Inventors: Hsiao Yun Lo, Yung-Chi Lin, Yang-Chih Hsueh, Tsang-Jiuh Wu, Wen-Chih Chiou
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Publication number: 20160256863Abstract: The present invention provides methods and designs of enclosed-channel reactor system for manufacturing catalysts or supports. Both of the configuration designs force the gaseous precursors and purge gas flow through the channel surface of reactor. The precursors will transform to thin film or particle catalysts or supports under adequate reaction temperature, working pressure and gas concentration. The reactor body is either sealed or enclosed for isolation from atmosphere. Another method using super ALD cycles is also proposed to grow alloy catalysts or supports with controllable concentration. The catalysts prepared by the method and system in the present invention are noble metals, such as platinum, palladium, rhodium, ruthenium, iridium and osmium, or transition metals such as iron, silver, cobalt, nickel and tin, while supports are silicon oxide, aluminum oxide, zirconium oxide, cerium oxide or magnesium oxide, or refractory metals, which can be chromium, molybdenum, tungsten or tantalum.Type: ApplicationFiled: May 17, 2016Publication date: September 8, 2016Inventors: Chi-Chung Kei, Bo-Heng Liu, Chien-Pao Lin, Chien-Nan Hsiao, Yang-Chih Hsueh, Tsong-Pyng Perng
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Patent number: 9381509Abstract: The present invention provides methods and designs of enclosed-channel reactor system for manufacturing catalysts or supports. Both of the configuration designs force the gaseous precursors and purge gas flow through the channel surface of reactor. The precursors will transform to thin film or particle catalysts or supports under adequate reaction temperature, working pressure and gas concentration. The reactor body is either sealed or enclosed for isolation from atmosphere. Another method using super ALD cycles is also proposed to grow alloy catalysts or supports with controllable concentration. The catalysts prepared by the method and system in the present invention are noble metals, such as platinum, palladium, rhodium, ruthenium, iridium and osmium, or transition metals such as iron, silver, cobalt, nickel and tin, while supports are silicon oxide, aluminum oxide, zirconium oxide, cerium oxide or magnesium oxide, or refractory metals, which can be chromium, molybdenum, tungsten or tantalum.Type: GrantFiled: July 23, 2013Date of Patent: July 5, 2016Assignee: NATIONAL APPLIED RESEARCH LABORATORIESInventors: Chi-Chung Kei, Bo-Heng Liu, Chien-Pao Lin, Chien-Nan Hsiao, Yang-Chih Hsueh, Tsong-Pyng Perng
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Publication number: 20150054174Abstract: An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad.Type: ApplicationFiled: October 9, 2014Publication date: February 26, 2015Inventors: Hsiao Yun Lo, Yung-Chi Lin, Yang-Chih Hsueh, Tsang-Jiuh Wu, Wen-Chih Chiou