Patents by Inventor Yang-Chih Shen
Yang-Chih Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250252048Abstract: A control circuit, comprising a storage circuit and a processor. The storage circuit is configured to store a retry sequence table and a plurality of read-voltage tables. The processor is coupled to the storage circuit, and is configured to access a memory comprising a plurality of blocks. When a read error occurs in a first block of the plurality of blocks, the processor sequentially uses the plurality of read-voltage tables to perform a retry test on the first block according to a retry sequence indicated by the retry sequence table. When a retry history data of the first block matches an adjustment condition, the processor adjusts the retry sequence indicated by the retry sequence table.Type: ApplicationFiled: January 15, 2025Publication date: August 7, 2025Inventors: Yang-Chih SHEN, Po Sheng CHOU, Bo-Yan JHAN
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Publication number: 20250156093Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.Type: ApplicationFiled: January 16, 2025Publication date: May 15, 2025Applicant: Silicon Motion, Inc.Inventors: Tsung-Chieh Yang, Chun-Chieh Kuo, Ching-Hui Lin, Yang-Chih Shen
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Patent number: 12236115Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.Type: GrantFiled: January 15, 2024Date of Patent: February 25, 2025Assignee: Silicon Motion, Inc.Inventors: Tsung-Chieh Yang, Chun-Chieh Kuo, Ching-Hui Lin, Yang-Chih Shen
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Publication number: 20240152288Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.Type: ApplicationFiled: January 15, 2024Publication date: May 9, 2024Applicant: Silicon Motion, Inc.Inventors: Tsung-Chieh Yang, Chun-Chieh Kuo, Ching-Hui Lin, Yang-Chih Shen
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Patent number: 11914873Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.Type: GrantFiled: May 19, 2021Date of Patent: February 27, 2024Assignee: Silicon Motion, Inc.Inventors: Tsung-Chieh Yang, Chun-Chieh Kuo, Ching-Hui Lin, Yang-Chih Shen
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Patent number: 11126558Abstract: A high-performance data storage device is disclosed. A controller updates a sub mapping table on the temporary storage in response to a write command of the non-volatile memory issued by a host. The mapping sub-table corresponds to a logical group involved in the write command and is downloaded from the non-volatile memory. When the mapping sub-table has not been completely downloaded to the temporary storage memory, the controller pushes the write command to a waiting queue to avoid dragging the performance of the data storage device.Type: GrantFiled: December 27, 2019Date of Patent: September 21, 2021Assignee: SILICON MOTION, INC.Inventors: Wei-Lin Kao, Yang-Chih Shen, Jian-Yu Chen
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Publication number: 20210271402Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.Type: ApplicationFiled: May 19, 2021Publication date: September 2, 2021Inventors: Tsung-Chieh Yang, Chun-Chieh Kuo, Ching-Hui Lin, Yang-Chih Shen
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Patent number: 11080203Abstract: High performance data storage device is disclosed, which has a memory controller dynamically updating mapping information on the temporary storage to manage physical space information mapped to a logical address recognized by a host. The memory controller uses a first bit to an Nth bit of the physical space information to indicate a physical space of the non-volatile memory or a cache address of the data cache space, without using additional bits to map the physical space information to the non-volatile memory or the data cache space, where N is a number greater than one. Among numbers formed by the first to the Nth bit, the memory controller uses numbers corresponding to non-existent physical space of the non-volatile memory to map the physical space information to the non-volatile memory or the data cache space.Type: GrantFiled: September 17, 2019Date of Patent: August 3, 2021Assignee: SILICON MOTION, INC.Inventors: Yang-Chih Shen, Shih-Chang Chang
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Patent number: 11048421Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.Type: GrantFiled: September 24, 2020Date of Patent: June 29, 2021Assignee: Silicon Motion, Inc.Inventors: Tsung-Chieh Yang, Chun-Chieh Kuo, Ching-Hui Lin, Yang-Chih Shen
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Patent number: 10990325Abstract: A write control method, an associated data storage device and the controller thereof are provided. The write control method includes: receiving one or more commands from a host device and executing the one or more commands, and performing determining operations to generate determining results; in response to the determining results, starting performing write collection; collecting and handling one or more write commands to buffer data of the one or more write commands through a buffer memory, and performing other determining operations to generate other determining results; in response to the other determining results, according to a quantity of one or more collected and handled write commands, determining whether data thereof has filled up a write buffer region of the buffer memory; and in response to the data having filled up the write buffer region, flushing the write buffer region to write the data therein into a non-volatile memory.Type: GrantFiled: October 2, 2019Date of Patent: April 27, 2021Assignee: Silicon Motion, Inc.Inventors: Yu-Han Hsiao, Yang-Chih Shen, Huan-Jung Yeh
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Publication number: 20210011643Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.Type: ApplicationFiled: September 24, 2020Publication date: January 14, 2021Inventors: Tsung-Chieh Yang, Chun-Chieh Kuo, Ching-Hui Lin, Yang-Chih Shen
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Patent number: 10824354Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.Type: GrantFiled: November 17, 2019Date of Patent: November 3, 2020Assignee: Silicon Motion, Inc.Inventors: Tsung-Chieh Yang, Chun-Chieh Kuo, Ching-Hui Lin, Yang-Chih Shen
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Patent number: 10783071Abstract: A data storage device with a non-volatile memory on which a garbage collection operation is segmented to be accomplished at separate time intervals. Host commands are inserted to be executed between the separate time intervals. A data swap stage or/and an F2H table update stage or/and an H2F table update stage for a garbage collection operation may be segmented to be performed at separate time intervals.Type: GrantFiled: November 20, 2018Date of Patent: September 22, 2020Assignee: Silicon Motion, Inc.Inventors: Ting-Hsing Wang, Yang-Chih Shen
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Publication number: 20200272574Abstract: High performance data storage device is disclosed, which has a memory controller dynamically updating mapping information on the temporary storage to manage physical space information mapped to a logical address recognized by a host. The memory controller uses a first bit to an Nth bit of the physical space information to indicate a physical space of the non-volatile memory or a cache address of the data cache space, without using additional bits to map the physical space information to the non-volatile memory or the data cache space, where N is a number greater than one. Among numbers formed by the first to the Nth bit, the memory controller uses numbers corresponding to non-existent physical space of the non-volatile memory to map the physical space information to the non-volatile memory or the data cache space.Type: ApplicationFiled: September 17, 2019Publication date: August 27, 2020Inventors: Yang-Chih SHEN, Shih-Chang CHANG
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Publication number: 20200272570Abstract: A high-performance data storage device is disclosed. A controller updates a sub mapping table on the temporary storage in response to a write command of the non-volatile memory issued by a host. The mapping sub-table corresponds to a logical group involved in the write command and is downloaded from the non-volatile memory. When the mapping sub-table has not been completely downloaded to the temporary storage memory, the controller pushes the write command to a waiting queue to avoid dragging the performance of the data storage device.Type: ApplicationFiled: December 27, 2019Publication date: August 27, 2020Inventors: Wei-Lin KAO, Yang-Chih SHEN, Jian-Yu CHEN
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Patent number: 10725902Abstract: A method for scheduling read commands, performed by a processing unit, includes at least the following steps: receiving a logical read command and a logical address; obtaining a high-level mapping table; obtaining a mapping table block according to the logical address and the high-level mapping table; obtaining a first physical address according to the logical address and the mapping table block; outputting an actual read command and the first physical address to a storage unit to obtain a data; and outputting the data which is responsive to the logical read command. The high-level mapping table includes a plurality of records, and one of the records is utilized to illustrate a second physical address of the mapping table block.Type: GrantFiled: July 10, 2018Date of Patent: July 28, 2020Assignee: Silicon Motion, Inc.Inventor: Yang-Chih Shen
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Patent number: 10642729Abstract: A data storage device with a non-volatile memory on which a garbage collection operation is segmented to be accomplished at separate time intervals. Host commands are inserted to be executed between the separate time intervals. A data swap stage or/and an F2H table update stage or/and an H2F table update stage for a garbage collection operation may be segmented to be performed at separate time intervals.Type: GrantFiled: November 2, 2017Date of Patent: May 5, 2020Assignee: Silicon Motion, Inc.Inventors: Ting-Hsing Wang, Yang-Chih Shen
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Patent number: 10628319Abstract: The invention introduces a method for caching and reading data to be programmed into a storage unit, performed by a processing unit, including at least the following steps. A write command for programming at least a data page into a first address is received from a master device via an access interface. It is determined whether a block of data to be programmed has been collected, where the block contains a specified number of pages. The data page is stored in a DRAM (Dynamic Random Access Memory) and cache information is updated to indicate that the data page has not been programmed into the storage unit, and to also indicate the location of the DRAM caching the data page when the block of data to be programmed has not been collected.Type: GrantFiled: November 16, 2018Date of Patent: April 21, 2020Assignee: Silicon Motion, Inc.Inventors: Yang-Chih Shen, Che-Wei Hsu
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Publication number: 20200110555Abstract: A write control method, an associated data storage device and the controller thereof are provided. The write control method includes: receiving one or more commands from a host device and executing the one or more commands, and performing determining operations to generate determining results; in response to the determining results, starting performing write collection; collecting and handling one or more write commands to buffer data of the one or more write commands through a buffer memory, and performing other determining operations to generate other determining results; in response to the other determining results, according to a quantity of one or more collected and handled write commands, determining whether data thereof has filled up a write buffer region of the buffer memory; and in response to the data having filled up the write buffer region, flushing the write buffer region to write the data therein into a non-volatile memory.Type: ApplicationFiled: October 2, 2019Publication date: April 9, 2020Inventors: Yu-Han Hsiao, Yang-Chih Shen, Huan-Jung Yeh
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Publication number: 20200081641Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.Type: ApplicationFiled: November 17, 2019Publication date: March 12, 2020Inventors: Tsung-Chieh Yang, Chun-Chieh Kuo, Ching-Hui Lin, Yang-Chih Shen