Abstract: The present application relates to a battery and an electronic device. The battery includes a first shell, a second shell, and a battery core. The first shell provides a receiving cavity. The battery core is disposed in the receiving cavity. The second shell is disposed on a side of the battery core away from the first shell, and the second shell is connected to the first shell. A support structure is provided at an outer surface of the second shell away from the battery core. The support structure is provided protruding from the outer surface of the second shell, and heat dissipation channels are formed between the support structure and the outer surface of the second shell.

Abstract: A stimulus-responsive micellar carrier, methods that may be associated with making a stimulus-responsive micellar carrier, and methods that may be associated with using a stimulus-responsive micellar carrier are disclosed. The stimulus-responsive micellar carrier comprises a cargo molecule, and a linear block copolymer having a hydrophilic block connected to a hydrophobic block by a stimulus-responsive junction moiety. The micellar carrier can be supplied to a patient body for therapeutic purposes, such as the treatment of cancerous tissue. A method of preparing or obtaining a stimulus-responsive micellar carrier may include preparing a polyethylene glycol material having an acetal end group and then preparing a block copolymer by forming a reaction mixture including the polyethylene glycol material, a cyclic carbonate monomer, and a base.

Abstract: An IQ generator capable of consuming lower power and occupying smaller die area. The IQ generator is configured without any synthesizer and divide-by-2 circuitry. The IQ generator may be configured to convert one or more phase outputs of a test tone generator (TTG) into I and Q signals. The IQ generator may receive as inputs differential outputs of a single phase of a TTG and/or multiple phase outputs of a TTG. The IQ generator may include one or more delay paths configured to generate the I and Q signals, and a calibration circuitry configured to compare the average pulse widths of the I and Q signals and provide one or more control signals to the one or more delay paths such that the I and Q signals are orthogonal in phase.

Abstract: An IQ generator capable of consuming lower power and occupying smaller die area. The IQ generator is configured without any synthesizer and divide-by-2 circuitry. The IQ generator may be configured to convert one or more phase outputs of a test tone generator (TTG) into I and Q signals. The IQ generator may receive as inputs differential outputs of a single phase of a TTG and/or multiple phase outputs of a TTG. The IQ generator may include one or more delay paths configured to generate the I and Q signals, and a calibration circuitry configured to compare the average pulse widths of the I and Q signals and provide one or more control signals to the one or more delay paths such that the I and signals are orthogonal in phase.

Abstract: A stimulus-responsive micellar carrier, methods that may be associated with making a stimulus-responsive micellar carrier, and methods that may be associated with using a stimulus-responsive micellar carrier are disclosed. The stimulus-responsive micellar carrier comprises a cargo molecule, and a linear block copolymer having a hydrophilic block connected to a hydrophobic block by a stimulus-responsive junction moiety. The micellar carrier can be supplied to a patient body for therapeutic purposes, such as the treatment of cancerous tissue. A method of preparing or obtaining a stimulus-responsive micellar carrier may include preparing a polyethylene glycol material having an acetal end group and then preparing a block copolymer by forming a reaction mixture including the polyethylene glycol material, a cyclic carbonate monomer, and a base.

Abstract: A stimulus-responsive micellar carrier, methods that may be associated with making a stimulus-responsive micellar carrier, and methods that may be associated with using a stimulus-responsive micellar carrier are disclosed. The stimulus-responsive micellar carrier comprises a cargo molecule, and a linear block copolymer having a hydrophilic block connected to a hydrophobic block by a stimulus-responsive junction moiety. The micellar carrier can be supplied to a patient body for therapeutic purposes, such as the treatment of cancerous tissue. A method of preparing or obtaining a stimulus-responsive micellar carrier may include preparing a polyethylene glycol material having an acetal end group and then preparing a block copolymer by forming a reaction mixture including the polyethylene glycol material, a cyclic carbonate monomer, and a base.

Abstract: A stimulus-responsive micellar carrier, methods that may be associated with making a stimulus-responsive micellar carrier, and methods that may be associated with using a stimulus-responsive micellar carrier are disclosed. The stimulus-responsive micellar carrier comprises a cargo molecule, and a linear block copolymer having a hydrophilic block connected to a hydrophobic block by a stimulus-responsive junction moiety. The micellar carrier can be supplied to a patient body for therapeutic purposes, such as the treatment of cancerous tissue. A method of preparing or obtaining a stimulus-responsive micellar carrier may include preparing a polyethylene glycol material having an acetal end group and then preparing a block copolymer by forming a reaction mixture including the polyethylene glycol material, a cyclic carbonate monomer, and a base.

Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

Abstract: A switching power amplifier includes: a first transistor controlled by a first digital signal to selectively output a first output signal; a second transistor controlled by a second digital signal to selectively output a second output signal; and a control circuit arranged to generate the second digital signal according to the first digital signal and a third digital signal; wherein the first output signal and the second output signal are outputted on a common connected node of the first transistor and the second transistor.

Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

Abstract: A data converting device includes: a data sampling circuit arranged to up-sample a digital signal to generate an up-sampling signal according to a clock signal; a voltage level generating circuit arranged to generate an adjustable voltage; and a signal converting circuit arranged to generate a converting signal according to the adjustable voltage and the up-sampling signal.

Abstract: An image processing device has an affinity calculating unit that handles each pixel in an image or each region including a plurality of pixels joined together, as a unit component, and determines a first affinity between each of the unit components and one of the unit components which is located in a periphery region of the image, a foreground region identifying unit that identifies, as a foreground region, a region made up of one or more of the unit components whose first affinities calculated by the affinity calculating unit are lower than a preset threshold, and a saliency measure output unit that determines a second affinity between each of the unit components in the image and the foreground region identified by the foreground region identifying unit, and outputs the second affinity as a saliency measure for each unit component.

Abstract: A signal converting device includes: a first converting circuit arranged to receive a first inputting signal; and a first capacitive circuit coupled between an output terminal of the first converting circuit and a reference voltage; wherein the first converting circuit is arranged to generate a first converting signal on the output terminal of the first converting circuit according to the first inputting signal.

Abstract: A digital transmitter includes: a plurality of converting devices arranged to generate a plurality of converting signals according to a plurality of digital input signals; a compensation device arranged to generate at least one compensation signal according to the plurality of digital input signals; and a combining circuit arranged to output an amplified output signal according to the plurality of converting signals and the at least one compensation signal.

Abstract: A digital transmitter includes: a plurality of converting devices arranged to generate a plurality of converting signals according to a plurality of digital input signals; a compensation device arranged to generate at least one compensation signal according to the plurality of digital input signals; and a combining circuit arranged to output an amplified output signal according to the plurality of converting signals and the at least one compensation signal.

Abstract: A switching power amplifier includes: a first transistor controlled by a first digital signal to selectively output a first output signal; a second transistor controlled by a second digital signal to selectively output a second output signal; and a control circuit arranged to generate the second digital signal according to the first digital signal and a third digital signal; wherein the first output signal and the second output signal are outputted on a common connected node of the first transistor and the second transistor.

Abstract: A signal converting device includes: a first converting circuit arranged to receive a first inputting signal; and a first capacitive circuit coupled between an output terminal of the first converting circuit and a reference voltage; wherein the first converting circuit is arranged to generate a first converting signal on the output terminal of the first converting circuit according to the first inputting signal.