Patents by Inventor Yang-Chuan Chen
Yang-Chuan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11646919Abstract: An IQ generator capable of consuming lower power and occupying smaller die area. The IQ generator is configured without any synthesizer and divide-by-2 circuitry. The IQ generator may be configured to convert one or more phase outputs of a test tone generator (TTG) into I and Q signals. The IQ generator may receive as inputs differential outputs of a single phase of a TTG and/or multiple phase outputs of a TTG. The IQ generator may include one or more delay paths configured to generate the I and Q signals, and a calibration circuitry configured to compare the average pulse widths of the I and Q signals and provide one or more control signals to the one or more delay paths such that the I and Q signals are orthogonal in phase.Type: GrantFiled: December 4, 2020Date of Patent: May 9, 2023Assignee: MEDIATEK Singapore Pte. Ltd.Inventors: Yang-Chuan Chen, Yuen Hui Chee, Osama Shanaa
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Publication number: 20210211335Abstract: An IQ generator capable of consuming lower power and occupying smaller die area. The IQ generator is configured without any synthesizer and divide-by-2 circuitry. The IQ generator may be configured to convert one or more phase outputs of a test tone generator (TTG) into I and Q signals. The IQ generator may receive as inputs differential outputs of a single phase of a TTG and/or multiple phase outputs of a TTG. The IQ generator may include one or more delay paths configured to generate the I and Q signals, and a calibration circuitry configured to compare the average pulse widths of the I and Q signals and provide one or more control signals to the one or more delay paths such that the I and signals are orthogonal in phase.Type: ApplicationFiled: December 4, 2020Publication date: July 8, 2021Applicant: MEDIATEK Singapore Pte. Ltd.Inventors: Yang-Chuan Chen, Yuen Hui Chee, Osama Shanaa
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Patent number: 9917586Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.Type: GrantFiled: June 2, 2017Date of Patent: March 13, 2018Assignee: MediaTek Inc.Inventors: Yang-Chuan Chen, Chi-Hsueh Wang, Hsiang-Hui Chang, Bo-Yu Lin
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Patent number: 9876501Abstract: A switching power amplifier includes: a first transistor controlled by a first digital signal to selectively output a first output signal; a second transistor controlled by a second digital signal to selectively output a second output signal; and a control circuit arranged to generate the second digital signal according to the first digital signal and a third digital signal; wherein the first output signal and the second output signal are outputted on a common connected node of the first transistor and the second transistor.Type: GrantFiled: May 2, 2014Date of Patent: January 23, 2018Assignee: MediaTek Inc.Inventors: Yang-Chuan Chen, Hsiang-Hui Chang
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Publication number: 20170272074Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.Type: ApplicationFiled: June 2, 2017Publication date: September 21, 2017Applicant: MediaTek Inc.Inventors: Yang-Chuan Chen, Chi-Hsueh Wang, Hsiang-Hui Chang, Bo-Yu Lin
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Patent number: 9698785Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.Type: GrantFiled: September 2, 2016Date of Patent: July 4, 2017Assignee: MediaTek Inc.Inventors: Yang-Chuan Chen, Chi-Hsueh Wang, Hsiang-Hui Chang, Bo-Yu Lin
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Patent number: 9577638Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.Type: GrantFiled: May 9, 2014Date of Patent: February 21, 2017Assignee: MediaTek Inc.Inventors: Yang-Chuan Chen, Chi-Hsueh Wang, Hsiang-Hui Chang, Bo-Yu Lin
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Publication number: 20160373243Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.Type: ApplicationFiled: September 2, 2016Publication date: December 22, 2016Inventors: Yang-Chuan Chen, Chi-Hsueh Wang, Hsiang-Hui Chang, Bo-Yu Lin
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Patent number: 9425796Abstract: A data converting device includes: a data sampling circuit arranged to up-sample a digital signal to generate an up-sampling signal according to a clock signal; a voltage level generating circuit arranged to generate an adjustable voltage; and a signal converting circuit arranged to generate a converting signal according to the adjustable voltage and the up-sampling signal.Type: GrantFiled: May 8, 2014Date of Patent: August 23, 2016Assignee: MEDIATEK INC.Inventors: Yang-Chuan Chen, Chih-Jung Chen, Hsiang-Hui Chang
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Patent number: 9191004Abstract: A signal converting device includes: a first converting circuit arranged to receive a first inputting signal; and a first capacitive circuit coupled between an output terminal of the first converting circuit and a reference voltage; wherein the first converting circuit is arranged to generate a first converting signal on the output terminal of the first converting circuit according to the first inputting signal.Type: GrantFiled: May 7, 2014Date of Patent: November 17, 2015Assignee: MEDIATEK INC.Inventor: Yang-Chuan Chen
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Patent number: 9118371Abstract: A digital transmitter includes: a plurality of converting devices arranged to generate a plurality of converting signals according to a plurality of digital input signals; a compensation device arranged to generate at least one compensation signal according to the plurality of digital input signals; and a combining circuit arranged to output an amplified output signal according to the plurality of converting signals and the at least one compensation signal.Type: GrantFiled: May 20, 2014Date of Patent: August 25, 2015Assignee: MEDIATEK INC.Inventors: Chi-Hsueh Wang, Yang-Chuan Chen, Hsiang-Hui Chang, Li-Shin Lai, Khurram Muhammad
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Publication number: 20140348269Abstract: A data converting device includes: a data sampling circuit arranged to up-sample a digital signal to generate an up-sampling signal according to a clock signal; a voltage level generating circuit arranged to generate an adjustable voltage; and a signal converting circuit arranged to generate a converting signal according to the adjustable voltage and the up-sampling signal.Type: ApplicationFiled: May 8, 2014Publication date: November 27, 2014Applicant: MEDIATEK INC.Inventors: Yang-Chuan Chen, Chih-Jung Chen, Hsiang-Hui Chang
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Publication number: 20140348265Abstract: A digital transmitter includes: a plurality of converting devices arranged to generate a plurality of converting signals according to a plurality of digital input signals; a compensation device arranged to generate at least one compensation signal according to the plurality of digital input signals; and a combining circuit arranged to output an amplified output signal according to the plurality of converting signals and the at least one compensation signal.Type: ApplicationFiled: May 20, 2014Publication date: November 27, 2014Applicant: MEDIATEK INC.Inventors: Chi-Hsueh Wang, Yang-Chuan Chen, Hsiang-Hui Chang, Li-Shin Lai, Khurram Muhammad
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Publication number: 20140348259Abstract: A signal converting device includes: a first converting circuit arranged to receive a first inputting signal; and a first capacitive circuit coupled between an output terminal of the first converting circuit and a reference voltage; wherein the first converting circuit is arranged to generate a first converting signal on the output terminal of the first converting circuit according to the first inputting signal.Type: ApplicationFiled: May 7, 2014Publication date: November 27, 2014Applicant: MEDIATEK INC.Inventor: Yang-Chuan Chen
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Publication number: 20140348279Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.Type: ApplicationFiled: May 9, 2014Publication date: November 27, 2014Applicant: MEDIATEK INC.Inventors: Yang-Chuan Chen, Chi-Hsueh Wang, Hsiang-Hui Chang, Bo-Yu Lin
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Publication number: 20140347127Abstract: A switching power amplifier includes: a first transistor controlled by a first digital signal to selectively output a first output signal; a second transistor controlled by a second digital signal to selectively output a second output signal; and a control circuit arranged to generate the second digital signal according to the first digital signal and a third digital signal; wherein the first output signal and the second output signal are outputted on a common connected node of the first transistor and the second transistor.Type: ApplicationFiled: May 2, 2014Publication date: November 27, 2014Applicant: Mediatek Inc.Inventors: Yang-Chuan Chen, Hsiang-Hui Chang
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Patent number: 8705657Abstract: A digital signal processing circuit includes a combining stage and an output stage. The combining stage is arranged to receive a plurality of non-overlapping clock signals having a same frequency but different phases, receive a plurality of first input bit streams, and generate a first output bit stream by combining the first input bit streams according to the non-overlapping clock signals. The output stage is arranged to generate an output according to the first output bit stream. A digital signal processing method includes: receiving a plurality of non-overlapping clock signals having a same frequency but different phases; receiving a plurality of first input bit streams; generating a first output bit stream by combining the first input bit streams according to the non-overlapping clock signals; and generating an output according to the first output bit stream.Type: GrantFiled: June 13, 2011Date of Patent: April 22, 2014Assignee: Mediatek Inc.Inventors: Jie-Wei Lai, Yang-Chuan Chen
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Publication number: 20120128092Abstract: A digital signal processing circuit includes a combining stage and an output stage. The combining stage is arranged to receive a plurality of non-overlapping clock signals having a same frequency but different phases, receive a plurality of first input bit streams, and generate a first output bit stream by combining the first input bit streams according to the non-overlapping clock signals. The output stage is arranged to generate an output according to the first output bit stream. A digital signal processing method includes: receiving a plurality of non-overlapping clock signals having a same frequency but different phases; receiving a plurality of first input bit streams; generating a first output bit stream by combining the first input bit streams according to the non-overlapping clock signals; and generating an output according to the first output bit stream.Type: ApplicationFiled: June 13, 2011Publication date: May 24, 2012Inventors: Jie-Wei Lai, Yang-Chuan Chen