Abstract: Provided is a semiconductor device including chip identification (ID) generation circuits. The semiconductor device may be a multi-chip package including a plurality of memory chips, and each of the memory chips includes a chip ID generation circuit configured to selectively modify a chip ID of a corresponding memory chip. The chip ID generation circuit determines the chip ID of the memory chip by testing the chip ID of the memory chip by using a mode register, and selectively programs the chip ID of the memory chip by using at least two fuse sets. The chip ID generation circuit may block an output of the chip ID of the memory chip when the memory chip is determined as a defective chip or is selected to stop its use.

Abstract: Provided is a semiconductor device including chip identification (ID) generation circuits. The semiconductor device may be a multi-chip package including a plurality of memory chips, and each of the memory chips includes a chip ID generation circuit configured to selectively modify a chip ID of a corresponding memory chip. The chip ID generation circuit determines the chip ID of the memory chip by testing the chip ID of the memory chip by using a mode register, and selectively programs the chip ID of the memory chip by using at least two fuse sets. The chip ID generation circuit may block an output of the chip ID of the memory chip when the memory chip is determined as a defective chip or is selected to stop its use.