Abstract: A liquid crystal display includes a first substrate, a gate line disposed on the first substrate and extending parallel to a major horizontal reference line of the display, and a plurality of pixel unit cells disposed on and tesslating a display area of the first substrate where each unit cell includes a first field generating electrode and a second field generating electrode with an insulating layer interposed therebetween, wherein a first one of the first and second field generating electrodes has a plurality of cutouts defined therein for producing corresponding liquid crystal domains, the plurality of cutouts each including a first inclined edge portion forming a first angle with the vertical reference line and a second inclined edge portion forming a second angle with the vertical reference line that is different from the first angle, wherein a ratio of a length of the first inclined edge portion to a length of the cutout is about 80% or more, and the density of the plurality of pixels is about 200 PPI o

Abstract: Provided is a method for reducing output data noise of a semiconductor apparatus which includes a plurality of output buffers to output data. The method includes the steps of: driving low data to a specific output buffer among the plurality of output buffers, and driving data transiting from a high level to a low level to the other output buffers; and measuring the magnitude of data noise occurring in output data of the specific output buffer, and deciding slew rates of the plurality of output buffers based on the measurement result.

Abstract: Provided is an MCP including a plurality chips stacked therein. Each of the chips includes a plurality of inductor pads configured to transmit power or signals, and at both sides of a reference inductor pad, a first and a second inductor pads are formed to generate magnetic fluxes in different directions from each other.

Abstract: A semiconductor integrated circuit apparatus includes a semiconductor substrate, a plurality of through-silicon vias (TSVs) formed in the semiconductor substrate, and an impedance path blocking unit located between the plurality of TSVs.

Abstract: A semiconductor memory apparatus includes a plurality of banks each having a plurality of cell mats; a plurality of power lines disposed over predetermined portions of each of the plurality of banks; a column control region disposed adjacent to at least one of sides of each bank which are perpendicular to an extending direction of the power lines; and a conductive plate disposed over the column control region and electrically connected to the plurality of power lines.

Abstract: A wireless signal transmitting/receiving apparatus for a semiconductor system is disclosed The apparatus includes a serializer/deserializer (SERDES) circuit and a coupling pad. The SERDES circuit outputs a parallel input signal as a serial signal during transmission, and outputs a serial input signal as a parallel signal during reception. The coupling pad generates an inductively coupled wireless signal according to the serial signal outputted from the SERDES circuit, and provides a signal generated by inductive coupling with an external device as the serial input signal of the SERDES circuit.

Abstract: An internal voltage generation method includes the steps of: setting first to third sections by using a reference voltage; determining to which section an internal voltage level corresponds, among the first to third sections; and generating the internal voltage by controlling a voltage pumping amount according to a section corresponding to the internal voltage level.

Abstract: A semiconductor integrated circuit includes a first voltage line to which a first ground voltage is applied, a second voltage line to which a second ground voltage is applied, a third voltage line to which a first power supply voltage is applied, and a coupling unit including a MOS transistor having a source coupled to the first voltage line, a drain coupled to the second voltage line, and a gate coupled to the third voltage line.

Abstract: An output circuit of a semiconductor apparatus having two different types of decoupling capacitors is presented. The output circuit includes a first pad, a second pad, a main output unit and a decoupling capacitor region. The first and second pads are configured to respectively provide a power supply voltage and a ground voltage. The main output unit is coupled to the first and second pads. One end of the decoupling capacitor region is coupled to the first pad and the other end is coupled to the second pad. The decoupling capacitor region includes a first decoupling capacitor region spaced apart from a portion of the main output unit by a first distance, and a second decoupling capacitor region spaced apart from the main output unit by a second distance which is greater than the first distance.

Abstract: A semiconductor integrated circuit apparatus includes a semiconductor substrate, a plurality of signal lines, and at least one interface member. The signal lines are disposed on the semiconductor substrate. The interface member is disposed in the semiconductor substrate between the adjacent signal lines among the signal lines to pierce the semiconductor substrate.

Abstract: Provided are a method for fabricating a capacitor and a semiconductor device using the same. The semiconductor device includes a MOS transistor capacitor, first and second plate capacitors, and a metal interconnection. The MOS transistor capacitor is arranged between a power supply and a ground. The first and second plate capacitors are arranged between the power supply and the ground. The metal interconnection is configured to connect the first and second plate capacitors.

Abstract: A semiconductor device includes a MOS capacitor including a gate, a source, and a drain, a cylinder capacitor including a top electrode, a dielectric layer, and a bottom electrode, and a metal interconnection that connects the gate to the bottom electrode.

Abstract: A semiconductor integrated circuit includes a first voltage line to which a first ground voltage is applied, a second voltage line to which a second ground voltage is applied, a third voltage line to which a first power supply voltage is applied, and a coupling unit including a MOS transistor having a source coupled to the first voltage line, a drain coupled to the second voltage line, and a gate coupled to the third voltage line.

Abstract: A semiconductor memory chip includes: a driving voltage reception unit configured to receive a power supply voltage and a ground voltage; a first data driving unit configured to be supplied with the power supply voltage and the ground voltage, and drive first data to output the driven first data through a first data line; a second data driving unit configured to be supplied with the power supply voltage and the ground voltage, and drive second data to output the driven second data through a second data line; and a MOS transistor coupled between the first data line and the second data line.

Abstract: A semiconductor memory apparatus includes a plurality of banks each having a plurality of cell mats; a plurality of power lines disposed over predetermined portions of each of the plurality of banks; a column control region disposed adjacent to at least one of sides of each bank which are perpendicular to an extending direction of the power lines; and a conductive plate disposed over the column control region and electrically connected to the plurality of power lines.

Abstract: Provided is an MCP including a plurality chips stacked therein. Each of the chips includes a plurality of inductor pads configured to transmit power or signals, and at both sides of a reference inductor pad, a first and a second inductor pads are formed to generate magnetic fluxes in different directions from each other.

Abstract: An output circuit of a semiconductor apparatus having two different types of decoupling capacitors is presented. The output circuit includes a first pad, a second pad, a main output unit and a decoupling capacitor region. The first and second pads are configured to respectively provide a power supply voltage and a ground voltage. The main output unit is coupled to the first and second pads. One end of the decoupling capacitor region is coupled to the first pad and the other end is coupled to the second pad. The decoupling capacitor region includes a first decoupling capacitor region spaced apart from a portion of the main output unit by a first distance, and a second decoupling capacitor region spaced apart from the main output unit by a second distance which is greater than the first distance.

Abstract: An apparatus for displaying includes a memory configured to store an image of a recorded material and an information of the recorded material, a displaying unit configured to display the recorded material stored in the memory, a recording managing unit configured to divide the recorded material into one or more recorded materials, and extract one or more start images of the respective divided recorded materials, and a controlling unit configured to control for a user to select a replay time point of the recorded material using the start image extracted by the recording managing unit.

Abstract: A device test handler and a method for operating the same provide a significant reduction of the picking up and placing time periods, and reduce possible damage to the devices being tested. Devices and methods embodying the invention facilitate room temperature and high temperature testing within one device test handler to maximize testing efficiency. A test handler embodying the invention may include a pre-heater for pre-heating the devices on a loading shuttle as the loading shuttle passes to a test chamber. An indexing device in a test chamber of the device is used for successively transferring the devices from a loading shuttle to the test socket, and tested devices from the test socket to an unloading shuttle. Heat supply means may be provided for supplying a high temperature heat to the test chamber when the devices are required to be tested in a hot state.

Abstract: A device test handler and a method for operating the same provide a significant reduction of the picking up and placing time periods, and reduce possible damage to the devices being tested. Devices and methods embodying the invention facilitate room temperature and high temperature testing within one device test handler to maximize testing efficiency. A test handler embodying the invention may include a pre-heater for pre-heating the devices on a loading shuttle as the loading shuttle passes to a test chamber. An indexing device in a test chamber of the device is used for successively transferring the devices from a loading shuttle to the test socket, and tested devices from the test socket to an unloading shuttle. Heat supply means may be provided for supplying a high temperature heat to the test chamber when the devices are required to be tested in a hot state.