Patents by Inventor Yang Hyeon Kwon

Yang Hyeon Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220180953
    Abstract: A storage device includes: a memory device including a plurality of memory cells configured to store data and a plurality of word lines connected to the plurality of memory cells and a memory controller in communication with the memory device and configured to control the memory device, including controlling the memory device to perform a read operation perform, upon a failure of the read operation on the memory cell, a read retry operation by changing the read voltage based on a history read table, and wherein the memory controller is further configured to update the history read table, upon a success of the read retry operation, based on whether the word line connected to the memory cell is a last programmed word line according to a program order among word lines connected to the group of memory cells.
    Type: Application
    Filed: June 10, 2021
    Publication date: June 9, 2022
    Inventors: Chung Un NA, Yang Hyeon KWON
  • Patent number: 10748639
    Abstract: A controller includes a processor suitable for performing a first erase operation on a target memory block; a tester suitable for performing a test operation to apply test voltages to selected points of word lines included in the target memory block; a counter suitable for counting the numbers of error memory cells sensed through the test voltages at the selected points; and a skipper suitable for setting test skip information based on the numbers of error memory cells.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: August 18, 2020
    Assignee: SK hynix Inc.
    Inventor: Yang-Hyeon Kwon
  • Publication number: 20190311775
    Abstract: A controller includes a processor suitable for performing a first erase operation on a target memory block; a tester suitable for performing a test operation to apply test voltages to selected points of word lines included in the target memory block; a counter suitable for counting the numbers of error memory cells sensed through the test voltages at the selected points; and a skipper suitable for setting test skip information based on the numbers of error memory cells.
    Type: Application
    Filed: November 20, 2018
    Publication date: October 10, 2019
    Inventor: Yang-Hyeon KWON
  • Patent number: 9524791
    Abstract: A method for operating a data storage device using, as a storage medium, a nonvolatile memory device including a memory cell array which is constructed by pages including data cells and flag cells for storing whether upper bit (MSB) data is stored in a data cell, includes searching a last programmed page in the case where recovery is made from a power failure to a normal state; determining whether the last programmed page is an upper bit (MSB) page to be accessed to store upper bit (MSB) data; and adjusting a flag cell read voltage for reading flag cells, in the case where the last programmed page is an upper bit (MSB) page.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: December 20, 2016
    Assignee: SK Hynix Inc.
    Inventors: Kyung Bum Kim, Yang Hyeon Kwon