Abstract: A semiconductor device includes: a substrate includes an active area; a first landing pad connected to the active area and disposed on the substrate; a second landing pad connected to the active area, and spaced apart from the first landing pad, wherein the second landing pad is disposed on the substrate; a first lower electrode disposed on the first landing pad and extending in a direction substantially perpendicular to the substrate; a second lower electrode disposed on the second landing pad and extending in the direction substantially perpendicular to the substrate; a dielectric layer extending along the first lower electrode and the second lower electrode; and an upper electrode disposed on the dielectric layer, wherein a first upper surface of the first landing pad is disposed below a second upper surface of the second landing pad with respect to a lower surface of the substrate.

Abstract: A semiconductor device is manufactured by forming a first insulating layer on a semiconductor substrate. First contact pads and second contact pads are formed that penetrate through the first insulating layer and are electrically connected to the semiconductor substrate. A second insulating layer is formed that has guide contact holes that expose upper surfaces of the first contact pads. An etch stopper is formed on bottoms and sidewalls of the guide contact holes of the second insulating layer. Bit lines are formed that are electrically connected to the semiconductor substrate by the second contact pads. The bit lines are electrically isolated from the first contact pads.

Abstract: A semiconductor device is manufactured by forming a first insulating layer on a semiconductor substrate. First contact pads and second contact pads are formed that penetrate through the first insulating layer and are electrically connected to the semiconductor substrate. A second insulating layer is formed that has guide contact holes that expose upper surfaces of the first contact pads. An etch stopper is formed on bottoms and sidewalls of the guide contact holes of the second insulating layer. Bit lines are formed that are electrically connected to the semiconductor substrate by the second contact pads. The bit lines are electrically isolated from the first contact pads.

Abstract: A semiconductor device is manufactured by forming a first insulating layer on a semiconductor substrate. First contact pads and second contact pads are formed that penetrate through the first insulating layer and are electrically connected to the semiconductor substrate. A second insulating layer is formed that has guide contact holes that expose upper surfaces of the first contact pads. An etch stopper is formed on bottoms and sidewalls of the guide contact holes of the second insulating layer. Bit lines are formed that are electrically connected to the semiconductor substrate by the second contact pads. The bit lines are electrically isolated from the first contact pads.

Abstract: An integrated circuit memory device is formed by forming an interlevel insulating layer on a substrate. A plurality of storage node contact holes are formed in the interlayer insulating layer and are arranged in a pattern. A plurality of contact plugs are formed in the plurality of storage node contact holes, respectively. A material layer is formed on the interlevel insulating layer that has a plurality of landing pad holes that expose the plurality of contact plugs, respectively, the plurality of landing pad holes are arranged in a pattern that is offset with respect to the pattern of the storage node contact holes. A plurality of landing pads are formed in the plurality of landing pad holes and are connected to the plurality of contact plugs, respectively. A plurality of storage nodes are formed that are connected to the plurality of landing pads, respectively.

Abstract: A semiconductor device is manufactured by forming a first insulating layer on a semiconductor substrate. First contact pads and second contact pads are formed that penetrate through the first insulating layer and are electrically connected to the semiconductor substrate. A second insulating layer is formed that has guide contact holes that expose upper surfaces of the first contact pads. An etch stopper is formed on bottoms and sidewalls of the guide contact holes of the second insulating layer. Bit lines are formed that are electrically connected to the semiconductor substrate by the second contact pads. The bit lines are electrically isolated from the first contact pads.

Abstract: An integrated circuit memory device is formed by forming an interlevel insulating layer on a substrate. A plurality of storage node contact holes are formed in the interlayer insulating layer and are arranged in a pattern. A plurality of contact plugs are formed in the plurality of storage node contact holes, respectively. A material layer is formed on the interlevel insulating layer that has a plurality of landing pad holes that expose the plurality of contact plugs, respectively, the plurality of landing pad holes are arranged in a pattern that is offset with respect to the pattern of the storage node contact holes. A plurality of landing pads are formed in the plurality of landing pad holes and are connected to the plurality of contact plugs, respectively. A plurality of storage nodes are formed that are connected to the plurality of landing pads, respectively.