Abstract: A power semiconductor device including a first gate electrode layer recessed into a semiconductor substrate, the first gate electrode layer being configured to extend in a first direction for a first length and a second gate electrode layer configured to extend in the first direction on a surface of the semiconductor substrate, the second gate electrode layer having a second length shorter than the first length, and configured to contact a first side surface of the first gate electrode layer.

Abstract: A printed circuit board includes: an insulating portion; a first pad disposed on the bottom of the insulating portion; a first solder resist layer disposed on the bottom of the insulating portion, covering at least a portion of the first pad, and having a first opening in at least a portion of the first pad; a first barrier layer disposed on a portion of the first pad corresponding to the first opening; a first surface treatment layer disposed on the first barrier layer; a second pad disposed on the top of the insulating portion; a second solder resist layer disposed on the top of the insulating portion, covering at least a portion of the second pad; a metal post disposed on the second pad; and a second barrier layer disposed between the second pad and the metal post.

Abstract: A printed circuit board includes an interconnection portion including one or more insulating layers, one or more interconnection layers, and one or more via layers and having a cavity penetrating through at least a portion of the one or more insulating layers, an electronic component disposed in the cavity, a first insulating material disposed in at least a portion of the cavity and burying at least a portion of the electronic component, a second insulating material disposed on the first insulating material, and a micro-via penetrating through at least a portion of the second insulating material and connected to the electronic component. The micro-via has a width smaller than at least one via among the one or more via layers.

Abstract: The present disclosure relates to an SNP marker set for dog identification and a dog identification method using the same. The present disclosure can accurately and easily readably identify individual dogs through the SNP markers on the gene and combinations of the SNPs based on the simple results of AA/AB/BB (Homozygote/Heterozygote/Homo mutant) by using 381 single nucleotide polymorphisms (SNPs) on the gene, thereby proving to be useful for animal individual identification.

Abstract: A power semiconductor device includes a semiconductor layer of silicon carbide (SiC), at least one trench that extends in one direction, a gate insulating layer disposed on at least an inner wall of the at least one trench, at least one gate electrode layer disposed on the gate insulating layer, a drift region disposed in the semiconductor layer at least on one side of the at least one gate electrode layer, a well region disposed in the semiconductor layer to be deeper than the at least one gate electrode layer, a source region disposed in the well region, and at least one channel region disposed in the semiconductor layer of one side of the at least one gate electrode layer between the drift region and the source region.

Abstract: A power semiconductor device includes a semiconductor layer of silicon carbide (SiC), at least one trench that extends in one direction, a gate insulating layer disposed on at least an inner wall of the at least one trench, at least one gate electrode layer disposed on the gate insulating layer, a drift region disposed in the semiconductor layer at least on one side of the at least one gate electrode layer, a well region disposed in the semiconductor layer to be deeper than the at least one gate electrode layer, a source region disposed in the well region, and at least one channel region disposed in the semiconductor layer of one side of the at least one gate electrode layer between the drift region and the source region.

Abstract: A multilayer electronic component includes a body including a dielectric layer and an internal electrode; and an external electrode disposed on the body, wherein the dielectric layer includes a rare earth element, a secondary phase of the rare earth element and a dielectric grain, wherein, when an average thickness of the dielectric layer is defined as td and a maximum size of the dielectric layer of a secondary phase of the rare earth element in the thickness direction is defined as D, the dielectric layer includes two or more secondary phases of a rare earth element satisfying D/td?0.2.

Abstract: A power semiconductor device includes a semiconductor layer of silicon carbide (SiC), at least one trench that extends in one direction, a gate insulating layer disposed on at least an inner wall of the at least one trench, at least one gate electrode layer disposed on the gate insulating layer, a drift region disposed in the semiconductor layer at least on one side of the at least one gate electrode layer, a well region disposed in the semiconductor layer to be deeper than the at least one gate electrode layer, a source region disposed in the well region, and at least one channel region disposed in the semiconductor layer of one side of the at least one gate electrode layer between the drift region and the source region.

Abstract: A ceramic electronic component includes a body including a dielectric layer and an internal electrode disposed alternately with the dielectric layer; and an external electrode disposed on the body, wherein the dielectric layer includes a first region extending from an interfacial surface with the internal electrode to 50 nm of the dielectric layer in an inward direction and a second region excluding the first region, and wherein, in the first region, an average content of In based on overall elements excluding oxygen is 0.5 at % or more and 2.0 at % or less, and an average content of Sn based on overall elements excluding oxygen is 0.5 at % or more and 1.75 at % or less.

Abstract: The present invention relates to a coupling-assist device for a bicycle crank arm, comprising: a main body open through upper and lower portions, the main body having a space formed to receive a crank arm to be inserted; a handle member extending from a lower portion of the main body; a support frame including a fixing part formed on a lower portion thereof and coupled with the upper portion of the main body, and a position adjusting hole that is open through to allow a tool to be passed therethrough and connected to the crank arm, wherein the position adjusting hole enables adjustment of position of the tool in up and down directions; and a support means.

Abstract: Proposed is a hybrid energy generation device using sunlight and solar heat including a photovoltaic panel in which a plurality of photovoltaic cells are arranged on a front side thereof, a first heat storage pipe having an inlet through which heat transfer fluid is introduced, and having a first slit hole formed on a side thereof in a longitudinal direction, a second heat storage pipe disposed to face the first heat storage pipe, having an outlet through which the heat transfer fluid is discharged, and having a second slit hole formed on a side thereof in a longitudinal direction, two or more third heat storage pipes arranged to connect the first heat storage pipe and the second heat storage pipe, and each having a third slit hole formed on a side thereof in a longitudinal direction, and a heat dissipation panel laminated on a back side of the PV panel.

Abstract: A power semiconductor device includes a semiconductor layer of silicon carbide (SiC), at least one trench that extends in one direction, a gate insulating layer disposed on at least an inner wall of the at least one trench, at least one gate electrode layer disposed on the gate insulating layer, a drift region disposed in the semiconductor layer at least on one side of the at least one gate electrode layer, a well region disposed in the semiconductor layer to be deeper than the at least one gate electrode layer, a source region disposed in the well region, and at least one channel region disposed in the semiconductor layer of one side of the at least one gate electrode layer between the drift region and the source region.

Abstract: A multilayer electronic component includes a body including a dielectric layer and an internal electrode; and an external electrode disposed on the body, wherein the dielectric layer includes a plurality of dielectric grains, and wherein the plurality of dielectric grains include one or more first dielectric grains in which a sum of lengths of defects in a dielectric grain is 150 nm or more.

Abstract: A power semiconductor device includes a plurality of gate electrodes configured to be recessed from a first surface of a semiconductor substrate to a second surface of the semiconductor substrate, the second surface being opposite to the first surface, an emitter region configured to make contact with a trench and the first surface, being provided between respective ones of the plurality of gate electrodes, and including impurities of a first conductive type, a collector region configured to make contact with the second surface, and including second impurities of a second conductive type opposite to the first conductive type, a floating region extending toward the second surface in an extension direction of the trench while surrounding a bottom surface of the trench, and including the second impurities, and a trench emitter region interposed between the plurality of gate electrodes in the trench.

Abstract: Disclosed is a power semiconductor device that includes a gate electrode recessed from a first surface of a semiconductor substrate to a second surface, disposed opposite to the first surface, of the semiconductor substrate, an emitter region, including impurities in a first conductive type, disposed in contact with a trench, in which the gate electrode is disposed, and the first surface, a collector region, including impurities in a second conductive type opposite to the first conductive type, disposed in contact with the second surface, a floating region, including the impurities in the second conductive type, extending toward the second surface in an extension direction of the trench while surrounding a bottom surface of the trench, and a trench emitter region interposed under the gate electrode in the trench.

Abstract: Proposed is a hybrid energy generation device using sunlight and solar heat including a photovoltaic panel in which a plurality of photovoltaic cells are arranged on a front side thereof, a first heat storage pipe having an inlet through which heat transfer fluid is introduced, and having a first slit hole formed on a side thereof in a longitudinal direction, a second heat storage pipe disposed to face the first heat storage pipe, having an outlet through which the heat transfer fluid is discharged, and having a second slit hole formed on a side thereof in a longitudinal direction, two or more third heat storage pipes arranged to connect the first heat storage pipe and the second heat storage pipe, and each having a third slit hole formed on a side thereof in a longitudinal direction, and a heat dissipation panel laminated on a back side of the PV panel.

Abstract: The present invention relates to a coupling-assist device for a bicycle crank arm, comprising: a main body open through upper and lower portions, the main body having a space formed to receive a crank arm to be inserted; a handle member extending from a lower portion of the main body; a support frame including a fixing part formed on a lower portion thereof and coupled with the upper portion of the main body, and a position adjusting hole that is open through to allow a tool to be passed therethrough and connected to the crank arm, wherein the position adjusting hole enables adjustment of position of the tool in up and down directions; and a support means.

Abstract: A dielectric ceramic composition and a multilayer ceramic electronic component are provided, the dielectric ceramic composition includes a barium titanate base material main component and a subcomponent, a microstructure after sintering includes a first crystal grain including 3 or less domain boundaries and a second crystal grain including 4 or more domain boundaries, and an area ratio of the second crystal grain to the total crystal grains is 20% or less.

Abstract: Proposed are a manufacturing method of a composite capacitive desalination electrode which can increase the desalination efficiency and as a new structure with more excellent mechanical and chemical resistance, and a composite capacitive desalination electrode and assembly. The manufacturing method includes the following steps: a) forming a composite microporous membrane by forming an ion exchange resin layer on a surface of the microporous membrane; and b) forming the composite microporous membrane prepared in the step a) on both sides of an electrode sheet, thereby producing a first unit including the composite microporous membrane and the electrode sheet. The steps are performed in a single process line by an in-line continuous process.