Abstract: The present invention relates to an output circuit. A first external power is supplied to be used as a second external power in a normal operating mode, and the supply of the power is shut off and an output driver is made to have a HIGH impedance state in a deep power down mode, by a control signal that is applied as different potentials in the normal operating mode and the deep power down mode. Therefore, it is possible to prevent consumption of internal current and introduction of a signal from the outside through a DQ terminal.

Abstract: The present invention relates to an output circuit. A first external power is supplied to be used as a second external power in a normal operating mode, an the supply of the power is shut off and an output driver is made to have a HIGH impedance state in a deep power down mode, by a control signal that is applied as different potentials in the normal operating mode and the deep power down mode. Therefore, it is possible to prevent consumption of internal current and introduction of a signal from the outside through a DQ terminal.

Abstract: A repair circuit includes a bit fail repair block for using the column and row addresses to determine whether they are fail addresses in order to decide whether bit repair for the fail addresses are to be performed, a row repair block for determining whether the row addresses are fail and deciding whether row repair for the row addresses are to be performed depending on the output of the bit fail repair block, and a plurality of column repair blocks for deciding whether column repair for the column addresses are to be performed and deciding whether a normal column driver must be selected, depending on the column address, column fuse boxes and an output signal of the bit fail repair block.

Abstract: The present invention relates to an output circuit. A first external power is supplied to be used as a second external power in a normal operating mode, an the supply of the power is shut off and an output driver is made to have a HIGH impedance state in a deep power down mode, by a control signal that is applied as different potentials in the normal operating mode and the deep power down mode. Therefore, it is possible to prevent consumption of internal current and introduction of a signal from the outside through a DQ terminal.

Abstract: A fail repair circuit in semiconductor memory devices is disclosed. The fail repair circuit can be applied to semiconductor memory devices for receiving a row address and a column address at a time without receiving them divisionally, and semiconductor memory devices operating as a single read mode and a single write mode with no burst or a page mode without address multiplexing.

Abstract: The present invention relates to an output line arrangement structure of a row decoding array used to determine a word line address of a plurality of memory cell arrays in a semiconductor memory device. The present invention can decrease an area when arranging the memory array, and can implement a high speed operation according to load reduction of a word line control signal, by arranging a part of output lines at one side end portion of a memory array, and another part thereof at the middle portion of the memory array (bit line divider), in a bus structure of word line enable and disable signals used for the row decoding array (main word line and sub-word line array constitution).