Abstract: The present disclosure provides a semiconductor device and a method for fabricating a semiconductor device. The semiconductor device includes a substrate, a metal gate layer over the substrate, a channel between a source region and a drain region in the substrate, and a ferroelectric layer, at least a portion of the ferroelectric layer is between the metal gate layer and the substrate, wherein the ferroelectric layer includes hafnium oxide-based material, the hafnium oxide-based material includes a first portion of hafnium oxide with orthorhombic phase, a second portion of hafnium oxide with monoclinic phase, and a third portion of the hafnium oxide with tetragonal phase, wherein a first volume of the first portion is greater than a second volume of the second portion, and the second volume of the second portion is greater than a third volume the third portion.

Abstract: Current sharing in a power system having multiple PSUs comprises generating and supplying a first power and a second power to a load, and sensing a remote voltage value received by the load based on an accumulation of the first and second powers. The method further comprises determining, by the first PSU, local voltage and current values of the first power, a real impedance value of the first PSU based on the remote voltage value and the local voltage and current values of the first power, and a virtual impedance value of the first PSU based on the real impedance value of the first PSU and a reference impedance value. The method further comprises controlling generation of the first power by the first PSU based on the virtual impedance value of the first PSU.

Abstract: A method for forming a crystalline high-k dielectric layer and controlling the crystalline phase and orientation of the crystal growth of the high-k dielectric layer during an anneal process. The crystalline phase and orientation of the crystal growth of the dielectric layer may be controlled using seeding sections of the dielectric layer serving as nucleation sites and using a capping layer mask during the anneal process. The location of the nucleation sites and the arrangement of the capping layer allow the orientation and phase of the crystal growth of the dielectric layer to be controlled during the anneal process. Based on the dopants and the process controls used the phase can be modified to increase the permittivity and/or the ferroelectric property of the dielectric layer.

Abstract: The present disclosure provides a semiconductor device and a method for forming a semiconductor device. The semiconductor device includes a substrate, and a first gate dielectric stack over the substrate, wherein the first gate dielectric stack includes a first ferroelectric layer, and a first dielectric layer coupled to the first ferroelectric layer, wherein the first ferroelectric layer includes a first portion made of a ferroelectric material in orthorhombic phase, a second portion made of the ferroelectric material in monoclinic phase, and a third portion made of the ferroelectric material in tetragonal phase, wherein a total volume of the second portion is greater than a total volume of the first portion, and the total volume of the first portion is greater than a total volume of the third portion.

Abstract: A method is provided of swapping code execution among multiple microcontroller code banks. The microcontroller has computer-readable memory, a central processing unit, and an interrupt controller. The method comprises executing an instruction to process a first pointer storing an address location of a first application within a first code bank of computer-readable memory. The first application is executed based on processing the first pointer. The method also comprises replacing the address location of the first application stored within the first pointer with an address location of a second application stored with a second code bank of the computer-readable memory. The instruction to process the first pointer is executed to process the address location of the second application to execute the second application without stopping operation of the interrupt controller.

Abstract: Current sharing in a power system having multiple PSUs comprises generating and supplying a first power and a second power to a load, and sensing a remote voltage value received by the load based on an accumulation of the first and second powers. The method further comprises determining, by the first PSU, local voltage and current values of the first power, a real impedance value of the first PSU based on the remote voltage value and the local voltage and current values of the first power, and a virtual impedance value of the first PSU based on the real impedance value of the first PSU and a reference impedance value. The method further comprises controlling generation of the first power by the first PSU based on the virtual impedance value of the first PSU.

Abstract: Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack of the NCFET and FE-FET devices includes a non-ferroelectric interfacial layer formed over the semiconductor channel, and a ferroelectric gate dielectric layer formed over the interfacial layer. The ferroelectric gate dielectric layer is formed by inserting dopant-source layers in between amorphous high-k dielectric layers and then converting the alternating sequence of dielectric layers to a ferroelectric gate dielectric layer by a post-deposition anneal (PDA). The ferroelectric gate dielectric layer has adjustable ferroelectric properties that may be varied by altering the precisely-controlled locations of the dopant-source layers using ALD/PEALD techniques. Accordingly, the methods described herein enable fabrication of stable NCFET and FE-FET FinFET devices that exhibit steep subthreshold slopes.

Abstract: A method includes forming a first semiconductor channel region and a second semiconductor channel region, with the second semiconductor channel region overlapping the first semiconductor channel region, forming a first gate dielectric on the first semiconductor channel region, and forming a second gate dielectric on the second semiconductor channel region. A dipole dopant is incorporated into a first one of the first gate dielectric and the second gate dielectric to a higher atomic percentage, and a second one of the first gate dielectric and the second gate dielectric has a lower atomic percentage of the dipole dopant. A gate electrode is formed on both of the first gate dielectric and the second gate dielectric. The gate electrode and the first gate dielectric form parts of a first transistor, and the gate electrode and the second gate dielectric form parts of a second transistor.

Abstract: A cantilever probe card and a probe module thereof are provided. The probe module includes a supporting board, a substrate disposed on the supporting board, a plurality of cantilever probes, and a plurality of fine adjustment members. The substrate has a non-planar shape and has a difference of warpage along a testing direction. One end of each of the cantilever probes is connected to the substrate, and another end of each of the cantilever probes is a free end. The fine adjustment members are spaced apart from each other and are disposed between the supporting board and the substrate. Each of the fine adjustment members is configured to be independently operable along the testing direction for changing a distance between the supporting board and the substrate. The substrate is deformable through at least one of the fine adjustment members so as to reduce the difference of warpage.

Abstract: An ophthalmic drug delivery carrier includes a resveratrol-encapsulating poly(?-caprolactone) (PCL) nanoparticle, metformin grafted on a surface of the resveratrol-encapsulating PCL nanoparticle, and a transacting activator of transcription (TAT) peptide grafted on the surface of the resveratrol-encapsulating PCL nanoparticle. A method for preparing the ophthalmic drug delivery carrier and a method for alleviating macular degeneration using the ophthalmic drug delivery carrier are also provided.

Abstract: A light scattering probe includes an arm segment, a main segment located at one side of the arm segment, and a testing segment connected to another side of the arm segment. The main segment has a soldering end portion and an extending end portion respectively located at two opposite sides thereof along a predetermined direction. The testing segment has an upright shape along the predetermined direction and includes a pinpoint portion and an upright portion that connects the pinpoint portion and the arm segment. The upright portion has a roughened surface arranged on an entirety of an outer surface thereof. The roughened surface has an arithmetic average roughness (Ra) within a range from 0.1 ?m to 1 ?m. Through the roughened surface, the testing segment only forms an observation point at the pinpoint portion in an observation process of a detection apparatus.

Abstract: A solder receiving probe includes an arm segment, a main segment located at one side of the arm segment, and a testing segment connected to another side of the arm segment. The main segment has a soldering end portion and an extending end portion respectively located at two opposite sides thereof along a predetermined direction. The main segment has a plurality of solder receiving holes that are arranged along a top edge of the soldering end portion and that are arranged in one row along an extending direction perpendicular to the predetermined direction. Any two of the solder receiving holes adjacent to each other are provided with one inner supporting arm therebetween. Each of the solder receiving holes can receive a solder, so that the solder does not climb across the solder receiving holes of the one row along the predetermined direction.

Abstract: A method of manufacturing a semiconductor device includes forming a dielectric layer conformally over a plurality of fins on a substrate, forming a first high-k layer conformally over the dielectric layer, and forming a flowable oxide over the first high-k layer. Forming the flowable oxide includes filling first trenches adjacent fins of the plurality of fins. The method further includes recessing the flowable oxide to form second trenches between adjacent fins of the plurality of fins, forming a second high-k layer over the first high-k layer and the flowable oxide, performing a planarization that exposes top surfaces of the plurality of fins, and recessing the dielectric layer to form a plurality of dummy fins that include remaining portions of the first and second high-k layers and the flowable oxide.

Abstract: A micro electro mechanical system (MEMS) probe includes an arm segment, a main segment, and a testing segment. The main segment is arranged at one side of the arm segment, the main segment defines a layout region arranged inside of an outer contour thereof, and the main segment has a soldering end portion and an extending end portion respectively arranged at two opposite sides of the distribution region along a predetermined direction. The testing segment has an upright shape along the predetermined direction and is connected to another side of the arm segment. The layout region has a plurality of thru-holes that occupy 3% to 70% of a region surroundingly defined by the outer contour. The layout region is spaced apart from the outer contour by a layout spacing that is less than or equal to an inner diameter of any one of the thru-holes.

Abstract: A climb-restricting probe includes an arm segment, a main segment located at one side of the arm segment, a testing segment connected to another side of the arm segment, and a climb-restricting ring. The main segment has a soldering end portion and an extending end portion respectively located at two opposite sides thereof along a predetermined direction. The testing segment has an upright shape along the predetermined direction. The climb-restricting ring surrounds the main segment along a top edge of the soldering end portion and protrudes from an outer surface of the main segment. The climb-restricting ring has a restriction height along the predetermined direction. The restriction height is within a range from 3 ?m to 50 ?m. The climb-restricting ring can block a solder from climbing past the climb-restricting ring along the predetermined direction.

Abstract: A light absorption probe includes an arm segment, a main segment located at one side of the arm segment, a testing segment connected to another side of the arm segment, and a light absorption coating layer. The main segment has a soldering end portion and an extending end portion respectively located at two opposite sides thereof along a predetermined direction. The testing segment has an upright shape along the predetermined direction and includes a pinpoint portion and an upright portion that connects the pinpoint portion and the arm segment. The light absorption coating layer covers the upright portion, and the pinpoint portion is exposed from the light absorption coating layer. Through the light absorption coating layer, the testing segment only forms an observation point at the pinpoint portion in an observation process of a detection apparatus.

Abstract: A cantilever probe module includes a plurality of first probes and a plurality of second probes. Each of the first probes includes a first arm segment, a first main segment, and a first testing segment, the latter two of which are respectively connected to two ends of the first arm segment. Each of the second probes includes a second arm segment, an extending segment and a second testing segment both respectively connected to two ends of the second arm segment, and a second main segment that is connected to the extending segment. A height of the extending segment is 5% to 50% of a height of the second main segment. When the first main segments of the first probes and the second main segments of the second probes are staggeredly fixed onto a substrate, the first testing segments and the second testing segments are arranged in one row.

Abstract: Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack includes a ferroelectric gate dielectric layer. An amorphous high-k dielectric layer and a dopant-source layer are deposited sequentially followed by a post-deposition anneal (PDA). The PDA converts the amorphous high-k layer to a polycrystalline high-k film with crystalline grains stabilized by the dopants in a crystal phase in which the high-k dielectric is a ferroelectric high-k dielectric. After the PDA, the remnant dopant-source layer may be removed. A gate electrode is formed over remnant dopant-source layer (if present) and the polycrystalline high-k film.

Abstract: A nano-crystalline high-k film and methods of forming the same in a semiconductor device are disclosed herein. The nano-crystalline high-k film may be initially deposited as an amorphous matrix layer of dielectric material and self-contained nano-crystallite regions may be formed within and suspended in the amorphous matrix layer. As such, the amorphous matrix layer material separates the self-contained nano-crystallite regions from one another preventing grain boundaries from forming as leakage and/or oxidant paths within the dielectric layer. Dopants may be implanted in the dielectric material and crystal phase of the self-contained nano-crystallite regions may be modified to change one or more of the permittivity of the high-k dielectric material and/or a ferroelectric property of the dielectric material.