Patents by Inventor Yang Lei

Yang Lei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11030436
    Abstract: A method of recognizing an object includes comparing a three-dimensional point cloud of the object to a three-dimensional candidate from a dataset to determine a first confidence score, and comparing color metrics of a two-dimensional image of the object to a two-dimensional candidate from the dataset to determine a second confidence score. The point cloud includes a color appearance calibrated from a white balance image, and the color appearance of the object is compared with the three-dimensional candidate. The first or second confidence score is selected to determine which of the three-dimensional candidate or the two-dimensional candidate corresponds with the object.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: June 8, 2021
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Yang Lei, Jian Fan, Jerry Liu
  • Publication number: 20210104071
    Abstract: A deep learning method employs a neural network having three sub-nets to classify and retrieve the most similar 3D model of an object, given a rough 3D model or scanned images. The most similar 3D model is present in a database and can be retrieved to use directly or as a reference to redesign the 3D model. The three sub-nets of the neural network include one dealing with object images and the other two dealing with voxel representations. Majority vote is used instead of view pooling to classify the object. A feature map and a list of top N most similar well-designed 3D models are also provided.
    Type: Application
    Filed: April 20, 2018
    Publication date: April 8, 2021
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Ruiting Shao, Yang Lei, Jian Fan, Jerry Liu
  • Publication number: 20210098395
    Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer.
    Type: Application
    Filed: December 14, 2020
    Publication date: April 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yu Kuo, Ching-Hua Hsieh, Chen-Hua Yu, Chung-Shi Liu, Yi-Yang Lei, Wei-Jie Huang
  • Publication number: 20210033842
    Abstract: A three-dimensional object modeling method may include applying a nonrotating nonuniform electric field to apply a dielectrophoretic torque to a three-dimensional object to rotate the three-dimensional object, capturing images of the object at different angles during rotation of the object and forming a three-dimensional model of the object based on the captured images.
    Type: Application
    Filed: April 27, 2018
    Publication date: February 4, 2021
    Inventors: Viktor Shkolnikov, Daixi Xin, Yang Lei
  • Patent number: 10867939
    Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yu Kuo, Ching-Hua Hsieh, Chen-Hua Yu, Chung-Shi Liu, Yi-Yang Lei, Wei-Jie Huang
  • Publication number: 20200368229
    Abstract: The present invention features interferon-free therapies for the treatment of HCV. Preferably, the treatment is over a shorter duration of treatment, such as no more than 12 weeks. In one aspect, the treatment comprises administering at least two direct acting antiviral agents to a subject with HCV infection, wherein the treatment lasts for 12 weeks and does not include administration of either interferon or ribavirin, and said at least two direct acting antiviral agents comprise (a) Compound 1 or a pharmaceutically acceptable salt thereof and (b) Compound 2 or a pharmaceutically acceptable salt thereof.
    Type: Application
    Filed: August 2, 2017
    Publication date: November 26, 2020
    Applicant: AbbVie Inc.
    Inventors: Christine Collins, Bo Fu, Abhishek Gulati, Jens Kort, Matthew Kosloski, Yang Lei, Chih-Wei Lin, Ran Liu, Federico Mensa, Iok Chan Ng, Tami Pilot-Matias, David Pugatch, Nancy S. Shulman, Roger Trinh, Rolando M. Viani, Stanley Wang, Zhenzhen Zhang
  • Publication number: 20200330460
    Abstract: The present invention features interferon-free therapies for the treatment of HCV. Preferably, the treatment is over a shorter duration of treatment, such as no more than 12 weeks. In one aspect, the treatment comprises administering at least two direct acting antiviral agents to a subject with HCV infection, wherein the treatment lasts for 12 weeks and does not include administration of either interferon or ribavirin, and said at least two direct acting antiviral agents comprise (a) Compound 1 or a pharmaceutically acceptable salt thereof and (b) Compound 2 or a pharmaceutically acceptable salt thereof.
    Type: Application
    Filed: August 30, 2018
    Publication date: October 22, 2020
    Applicant: AbbVie Inc.
    Inventors: Christine Collins, Emily O. Dumas, Bo Fu, Abhishek Gulati, Yiran Bonnie Hu, Jens Kort, Matthew Kosloski, Preethi Krishnan, Yang Lei, Chih-Wei Lin, Ran Liu, Frederico Mensa, Iok Chan Ng, Tami Pilot-Matias, David Pugatch, Susan Rhee, Nancy S. Shulman, Roger Trinh, Rolando M. Viani, Stanley Wang, Zhenzhan Zhang
  • Patent number: 10790252
    Abstract: Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a plurality of contact pads over a substrate, and forming an insulating material over the plurality of contact pads and the substrate. The insulating material is patterned to form an opening over each of the plurality of contact pads, and the plurality of contact pads is cleaned. The method includes forming an under-ball metallization (UBM) structure over the plurality of contact pads and portions of the insulating material. Cleaning the plurality of contact pads recesses a top surface of each of the plurality of contact pads.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yi-Yang Lei, Szu-Yu Yeh, Yu-Ren Chen, Hung-Jui Kuo, Chung-Shi Liu
  • Publication number: 20200222397
    Abstract: The present invention features interferon-free therapies for the treatment of HCV. Preferably, the treatment is over a shorter duration of treatment, such as no more than 16 weeks, alternatively no more than 12 weeks, or alternatively no more than 8 weeks. In one aspect, the treatment comprises administering at least two direct acting antiviral agents to a subject with HCV infection, wherein the treatment lasts for 16, 12, or 8 weeks and does not include administration of either interferon or ribavirin, and said at least two direct acting antiviral agents comprise (a) Compound 1 or a pharmaceutically acceptable salt thereof and (b) Compound 2 or a pharmaceutically acceptable salt thereof.
    Type: Application
    Filed: July 20, 2018
    Publication date: July 16, 2020
    Applicant: AbbVie Inc.
    Inventors: Christine Collins, Bo Fu, Abhishek Gulati, Jens Kort, Matthew Kosloski, Yang Lei, Chih-Wei Lin, Ran Liu, Federico Mensa, Iok Chan Ng, Tami Pilot-Matias, David Pugatch, Nancy S. Shulman, Roger Trinh, Rolando M. Viani, Stanley Wang, Zhenzhen Zhang
  • Publication number: 20200168568
    Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer.
    Type: Application
    Filed: June 14, 2019
    Publication date: May 28, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Yu Kuo, Ching-Hua Hsieh, Chen-Hua Yu, Chung-Shi Liu, Yi-Yang Lei, Wei-Jie Huang
  • Publication number: 20200152599
    Abstract: A method of manufacturing a semiconductor structure is provided. The method includes providing a first substrate including a plurality of conductive bumps disposed over the first substrate; providing a second substrate; disposing a patterned adhesive over the first substrate, wherein at least a portion of the plurality of conductive bumps is exposed through the patterned adhesive; bonding the first substrate with the second substrate; and singulating a chip from the first substrate.
    Type: Application
    Filed: January 14, 2020
    Publication date: May 14, 2020
    Inventors: ALEXANDER KALNITSKY, YI-YANG LEI, HSI-CHING WANG, CHENG-YU KUO, TSUNG LUNG HUANG, CHING-HUA HSIEH, CHUNG-SHI LIU, CHEN-HUA YU, CHIN-YU KU, DE-DUI LIAO, KUO-CHIO LIU, KAI-DI WU, KUO-PIN CHANG, SHENG-PIN YANG, ISAAC HUANG
  • Publication number: 20200125830
    Abstract: A method of recognizing an object includes comparing a three-dimensional point cloud of the object to a three-dimensional candidate from a dataset to determine a first confidence score, and comparing color metrics of a two-dimensional image of the object to a two-dimensional candidate from the dataset to determine a second confidence score. The point cloud includes a color appearance calibrated from a white balance image, and the color appearance of the object is compared with the three-dimensional candidate. The first or second confidence score is selected to determine which of the three-dimensional candidate or the two-dimensional candidate corresponds with the object.
    Type: Application
    Filed: April 27, 2017
    Publication date: April 23, 2020
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Yang Lei, Jian Fan, Jerry Liu
  • Publication number: 20200051949
    Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.
    Type: Application
    Filed: October 17, 2019
    Publication date: February 13, 2020
    Inventors: Hui-Jung Tsai, Yun Chen Hsieh, Jyun-Siang Peng, Tai-Min Chang, Yi-Yang Lei, Hung-Jui Kuo, Chen-Hua Yu
  • Patent number: 10535629
    Abstract: A method of manufacturing a semiconductor structure includes receiving a first substrate including an IMD layer disposed over the first substrate and a plurality of conductive bumps disposed in the IMD layer; receiving a second substrate; disposing a patterned adhesive over the first substrate, wherein at least a portion of the IMD layer is exposed through the patterned adhesive; and bonding the first substrate with the second substrate, wherein a top surface of the at least portion of the IMD layer is exposed through the patterned adhesive after bonding the first substrate with the second substrate.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Alexander Kalnitsky, Yi-Yang Lei, Hsi-Ching Wang, Cheng-Yu Kuo, Tsung Lung Huang, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu, Chin-Yu Ku, De-Dui Liao, Kuo-Chio Liu, Kai-Di Wu, Kuo-Pin Chang, Sheng-Pin Yang, Isaac Huang
  • Publication number: 20200013750
    Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.
    Type: Application
    Filed: September 19, 2019
    Publication date: January 9, 2020
    Inventors: Hui-Jung Tsai, Yun Chen Hsieh, Jyun-Siang Peng, Tai-Min Chang, Yi-Yang Lei, Hung-Jui Kuo, Chen-Hua Yu
  • Patent number: 10522501
    Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Jung Tsai, Yun Chen Hsieh, Jyun-Siang Peng, Tai-Min Chang, Yi-Yang Lei, Hung-Jui Kuo, Chen-Hua Yu
  • Publication number: 20190381630
    Abstract: A polishing pad, a polishing apparatus and a method of manufacturing a semiconductor package using the same are provided. In some embodiments, a polishing pad includes a sub-pad portion and a top pad portion over the sub-pad portion. The top pad portion includes a plurality of grooves having a first width and a plurality of openings having a second width different from the first width, and the openings are located in a center zone of the polishing pad.
    Type: Application
    Filed: June 15, 2018
    Publication date: December 19, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Cheng Wang, Ching-Hua Hsieh, Yi-Yang Lei
  • Publication number: 20190157240
    Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.
    Type: Application
    Filed: July 6, 2018
    Publication date: May 23, 2019
    Inventors: Hui-Jung Tsai, Yun Chen Hsieh, Jyun-Siang Peng, Tai-Min Chang, Yi-Yang Lei, Hung-Jui Kuo, Chen-Hua Yu
  • Patent number: 10269747
    Abstract: Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a plurality of contact pads over a substrate, and forming an insulating material over the plurality of contact pads and the substrate. The insulating material is patterned to form an opening over each of the plurality of contact pads, and the plurality of contact pads is cleaned. The method includes forming an under-ball metallization (UBM) structure over the plurality of contact pads and portions of the insulating material. Cleaning the plurality of contact pads recesses a top surface of each of the plurality of contact pads.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yi-Yang Lei, Szu-Yu Yeh, Yu-Ren Chen, Hung-Jui Kuo, Chung-Shi Liu
  • Publication number: 20190115313
    Abstract: A method of manufacturing a semiconductor structure includes receiving a first substrate including an IMD layer disposed over the first substrate and a plurality of conductive bumps disposed in the IMD layer; receiving a second substrate; disposing a patterned adhesive over the first substrate, wherein at least a portion of the IMD layer is exposed through the patterned adhesive; and bonding the first substrate with the second substrate, wherein a top surface of the at least portion of the IMD layer is exposed through the patterned adhesive after bonding the first substrate with the second substrate.
    Type: Application
    Filed: December 21, 2018
    Publication date: April 18, 2019
    Inventors: ALEXANDER KALNITSKY, YI-YANG LEI, HSI-CHING WANG, CHENG-YU KUO, TSUNG LUNG HUANG, CHING-HUA HSIEH, CHUNG-SHI LIU, CHEN-HUA YU, CHIN-YU KU, DE-DUI LIAO, KUO-CHIO LIU, KAI-DI WU, KUO-PIN CHANG, SHENG-PIN YANG, ISAAC HUANG