Abstract: Apparatuses and techniques for performing serialized update procedures during a refresh period are described. In example aspects, a memory device performs a normal refresh operation, which refreshes multiple rows simultaneously. The refreshed rows are associated with different refresh sections and different column segments. While refreshing the rows and prior to an end of a refresh cycle time (tRFC), the memory device updates, in a serialized manner, usage-based-disturbance data that is stored within the refreshed rows. In particular, the memory device performs, in series, multiple update procedures, which overwrites values of the usage-based-disturbance data that are stored within the refreshed rows. For example, the multiple update procedures can set values of activation counts that are stored within the refreshed rows to a predetermined value.

Abstract: A nail polish glue and a preparation method and application thereof are provided. The nail polish glue includes the following components in parts by weight: 15-57 parts of an acrylate prepolymer, 20-52 parts of an acrylate active monomer, 5-10 parts of a photoinitiator, 5-10 parts of mercaptan, 5-10 parts of an additive, and 3-8 parts of a colorant. The nail polish glue of the present disclosure has low odor and environmental friendliness, is convenient to operate and package, can be directly applied without using a primer and a seal, and has the adhesion of the primer and the gloss retention of the seal. Through reasonable collocation and mutual complement of the amount of components, excellent mechanical properties including hardness, adhesion and wear resistance, which are significantly improved, are effectively achieved.

Abstract: Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

Abstract: An apparatus for detecting beam failure for a beam failure detection reference signal set of a serving cell includes: a receiver configured to receive a beam failure instance indication in each of two beam failure detection reference signal sets configured for a serving cell; and processor circuitry configured to: increment, when the receiver receives a beam failure instance indication in a BFD-RS set which is included in the two BFD-RS sets, a beam failure indication count of the BFD-RS set by 1, trigger, in a case where the beam failure indication count of the BFD-RS set is greater than or equal to a beam failure instance maximum count for BFD-RS set, beam failure recovery for the BFD-RS set of the serving cell.

Abstract: Systems, apparatuses, and methods related to bloom filter implementation into a controller are described. A memory device is coupled to a memory controller. The memory controller is configured to implement a counting bloom filter, increment the counting bloom filter in response to a row activate command of the memory device, determine whether a value of the counting bloom filter exceeds a threshold value, and perform an action in response to the value exceeding the threshold value.

Abstract: A request for registration by a User Equipment (UE) to a cellular network is handled. The geographical coverage of the cellular network is divided into a plurality of tracking areas, each tracking area having a respective identifier. A registration request message is communicated from the UE to the cellular network via an access node. Where the registration request is rejected, a registration rejection message is communicated in response. The registration request message and/or the registration rejection message includes the identifier for each of one or more tracking areas to which the respective message applies.

Abstract: Embodiments of the present disclosure provide a half-bridge flyback converter, a control method, and a control circuit. The control method includes: controlling a second primary switching transistor to be ON for a first duration in a first switching period in a case where the half-bridge flyback converter operates in a free resonant state, and in response to detecting, based on sampled voltage information of a secondary power circuit, that the second primary switching transistor is turned on, controlling a secondary switching transistor to be ON for a second duration, such that the half-bridge flyback converter is reverse-magnetized to generate a negative magnetizing current, and thus a voltage across the first primary switching transistor is reduced to zero. By controlling the first primary switching transistor to turn on, zero-voltage switching of the first primary switching transistor is achieved. With the method, noise of the half-bridge flyback converter is reduced.

Abstract: Embodiments of this application disclose a blockchain key-based data processing method and apparatus. The method includes obtaining communication channels respectively communicating with N clients, and respectively performing key shard negotiation with the N clients to obtain a local private key shard and a complete public key; receiving signature requests transmitted by M?1 clients in the N clients, and obtaining identity association information in the M?1 signature requests; if the identity association information in the M?1 signature requests is legitimate identity information, determining a client that is in the M?1 clients as a target client, and obtaining service execution data associated with the target client; and if the service execution data conforms to a risk management policy corresponding to identity association information of the target client, jointly participating in joint signature processing on the blockchain service with the M?1 clients.

Abstract: Methods, systems, and devices related to mapping a plurality of pairs of bits of a memory transfer block (MTB) to a plurality of linked (LK) die input/output (LDIO) lines coupling a LK die to an interface (IF) die. The plurality of pairs of bits of the MTB can be communicated from the LK die to the IF die via the plurality of LDIO lines. Responsive to a failure of one of the plurality of LDIO lines, a Bose-Chaudhuri-Hocquenghem (BCH) error correction can be performed on the pairs of bits mapped to the failed LDIO line. Each of the plurality of pairs of bits is a respective symbol for the BCH error correction.

Abstract: An exposure control method includes: calculating a long-exposure brightness mean value of pixels of darker (N?X) kinds of brightness among N kinds of brightness values of a long exposure image, wherein a total number of pixels of brightest X kinds of brightness values among the N kinds of brightness values is a long-exposure bright pixel number; when the long-exposure brightness mean value doesn't approximate to a long-exposure target brightness mean value, adjusting exposure setting for generating/modifying the long exposure image to make the two brightness mean values be similar/equal; determining brightest K pixels of a short exposure image, wherein the K is equal to the long-exposure bright pixel number; calculating a short-exposure brightness mean value; and when the short-exposure brightness mean value doesn't approximate to a short-exposure target brightness mean value, adjusting exposure setting for generating/modifying the short exposure image to make the two brightness mean values be similar/equal.

Abstract: A value associated with a number of accesses of a word line and a length of said accesses may be stored on said word line. A timer may provide a periodic signal that increments a counter to update the value. The updated value may then be written back to the word line. In some examples, a memory device including the word lines may have a specification that prevents the word line from closing prior to writing the updated value to the word line.

Abstract: A message transmission apparatus, applicable to a first integrated access and backhaul node (IAB-node) includes: a receiver configured to: receive a second radio resource control (RRC) reconfiguration message for path migration of a second IAB-node while the first IAB-node is still connected with source parent node, the second radio resource control (RRC) reconfiguration message being transmitted by a donor central unit (donor-CU), the second IAB-node is a downstream child node of the first IAB-node; and receive a first RRC reconfiguration message for path migration of the first IAB-node, the first RRC reconfiguration message being transmitted by the donor-CU; and a transmitter configured to forward, to the second IAB-node, the second RRC reconfiguration message which is withhold until random access of the first IAB-node is successful.

Abstract: Apparatuses and techniques for implementing usage-based disturbance (UBD) counter repair are described. In example implementations, a memory device includes multiple memory rows, multiple corresponding UBD counters, a register, and a spare UBD counter. If a UBD counter is faulty, logic can substitute the spare UBD counter. To do so, the logic can store a row address corresponding to the faulty UBD counter in the register. The logic can increment a value in the spare UBD counter responsive to a row activation corresponding to the stored row address. A mitigation procedure on a row that may be affected by the activation can be performed based on the value. A host device can control, at least partially, the UBD counter repair process. In these manners, a repair of a faulty UBD counter can be accomplished faster and/or with fewer resources as compared to replacing a memory row and corresponding UBD counter.

Abstract: Apparatuses and techniques for reporting multiple events associated with mitigating usage-based disturbance are described. In an example aspect, a memory device can report to a memory controller various events associated with mitigating usage-based disturbance. This includes notifying the memory controller of events associated with a first event category and alerting the memory controller of events associated with a second event category. For events associated with the first event category, there can be a smaller risk of an alert condition occurring if the memory controller does not take action. For events associated with the second event category, there can be a larger risk of an alert condition occurring if the memory controller does not take action. By reporting these multiple events by category, the memory device empowers the memory controller to take appropriate action and efficiently manage available resources for mitigating usage-based-disturbance.

Abstract: Apparatuses and techniques for implementing collision avoidance for bank-shared circuitry that supports usage-based disturbance mitigation are described. A memory device includes bank-shared circuitry coupled to multiple banks. The bank-shared circuitry can support usage-based disturbance mitigation. By using the bank-shared circuitry to service multiple banks, the memory device can have a smaller footprint and can be cheaper to manufacture compared to other memory devices with circuitry dedicated for each bank. To avoid conflicts associated with some sequences of commands that may relate to a same bank or different banks and utilize the bank-shared circuitry, the memory controller applies an appropriate timing offset (or delay) between commands. The timing offset allows the memory device time to finish utilizing the bank-shared circuitry for usage-based disturbance mitigation prior to utilizing the bank-shared circuitry in accordance with a subsequent command.

Abstract: Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

Abstract: Apparatuses and techniques are described implementing power-efficient monitoring for usage-based-disturbance mitigation. In a first aspect, a memory device takes a less strict approach for monitoring worse-case conditions associated with usage-based disturbance. In particular, the memory device conserves power by foregoing updating a list of rows associated with worse-case conditions until an unlisted row has a substantially worse condition than any one of the listed rows. This decreases how often the memory device expends power to update the list. In an optional second aspect, the memory device performs a partial bit-width comparison operation to evaluate the “substantially worse” criterion. The partial bit-width comparison enables a comparator to be implemented with a smaller footprint and operate with less power as compared to a comparator that is capable of performing a full bit-width comparison operation.

Abstract: The present disclosure provides systems and methods for assessing a mental state of a subject in a single session or over multiple different sessions, using for example an automated module to present and/or formulate at least one query based in part on one or more target mental states to be assessed. The query may be configured to elicit at least one response from the subject. The query may be transmitted in an audio, visual, and/or textual format to the subject to elicit the response. Data comprising the response from the subject can be received. The data can be processed using one or more individual, joint, or fused models. One or more assessments of the mental state associated with the subject can be generated for the single session, for each of the multiple different sessions, or upon completion of one or more sessions of the multiple different sessions.

Abstract: Described apparatuses and methods relate to a bank-level self-refresh for a memory system. A memory device can include logic that implements self-refresh operations in the memory device. The logic may perform self-refresh operations on a set of banks of the memory device that is less than all banks within the memory device. The set of banks of the memory device may be determined such that the peak current in a power distribution network of the memory device is bounded when the self-refresh operation is performed. Accordingly, bank-level self-refresh can reduce a cost of the memory device of a memory system by enabling use of a less complicated power distribution network. The bank-level self-refresh may also be implemented with different types of refresh operations. Amongst other scenarios, bank-level self-refresh can be deployed in memory-expansion environments.

Abstract: Apparatuses and techniques for implementing shareable usage-based disturbance circuitry are described. Shareable usage-based disturbance circuitry includes circuits (e.g., shared circuits) that manage usage-based disturbance across at least two sections of a bank of memory within a die of a memory device. In example implementations, the shareable usage-based disturbance circuitry includes a counter circuit and/or an error-correction-code circuit that is coupled to sense amplifiers associated with two neighboring sections. With the shareable usage-based disturbance circuitry, dies within the memory device can be cheaper to manufacture, can consume less power, and can have a smaller footprint with less complex signal routing compared to other dies with other circuits dedicated to mitigating usage-based disturbance within each section.