Abstract: A donor device, applicable to an F1-terminating donor-CU of a mobile IAB node, includes: a receiver configured to receive first indication information, the first indication information comprising identity information related to a third donor-CU which is an RRC-terminating donor-CU after migration or radio link failure recovery of the mobile IAB node; and a transmitter configured to transmit second indication information for indicating a context of a traffic to the third donor-CU.

Abstract: Aspects of the subject technology provide for generation of a self-voice signal by an electronic device that is operating in an active noise cancellation mode. In this way, during a phone call, a video conference, or while listening to audio content, a user of the electronic device may benefit from active cancellation of ambient noise while still being able to hear their own voice when they speak. In various implementations described herein, the concurrent self-voice and automatic noise cancellation features are facilitated by accelerometer-based control of sidetone and/or active noise cancellation operations.

Abstract: In an embodiment, content data delivery to a requesting device in a content delivery network (CDN) may be handled by a server device using a content cache of a computing device associated with the server device. The computing device may be a component of, local to, and/or directly connected to the server device. The server device receives a request to deliver the content data, determines that the location of the content data is in the content cache, and responsive to this determination, sends instructions to the computing device to provide the content data to the requesting device. In one embodiment, the server device may acquire and provide the content data to the computing device for storage in the content cache, before or in response to receiving the request to deliver the content data.

Abstract: Apparatuses and techniques for handling faulty usage-based-disturbance data are described. In an example aspect, a memory device uses a report flag to indicate that an address of a row that corresponds to the faulty usage-based-disturbance data is logged at a global-bank level and is accessible by a host device. The report flag also enables the memory device to avoid reporting another error until the host device has cleared information associated with a previously-reported error. In another example aspect, the memory device temporarily prevents usage-based-disturbance mitigation from being performed based on the faulty usage-based-disturbance data. This means that if the faulty usage-based-disturbance data would otherwise trigger refreshing of one or more rows that are proximate to the row corresponding to the faulty usage-based-disturbance data, the memory device does not perform these refresh operations.

Abstract: Apparatuses and techniques for logging a memory address associated with faulty usage-based disturbance data are described. In an example aspect, a memory device can detect, at a local-bank level, a fault associated with usage-based disturbance data. This detection enables the memory device to log a row address associated with the faulty usage-based disturbance data. To avoid increasing a complexity and/or a size of the memory device, some implementations of the memory device can perform the address logging at the multi-bank level with the assistance of an engine, such as a test engine. The memory device stores the logged address in at least one mode register to communicate the fault to a memory controller. With the logged address, the memory controller can initiate a repair procedure to fix the faulty usage-based disturbance data.

Abstract: A random access apparatus, applicable to a terminal equipment, includes first processor circuitry, wherein the first processor circuitry is configured to determine a random access type according to configuration information of a bandwidth part (BWP) for random access selected by the terminal equipment and downlink reference signal received power measured by the terminal equipment, perform selection of random access resources, and transmit an initial message of random access on the random access resources.

Abstract: Apparatuses and methods for per-row count based refresh target identification with sorting. A memory includes a number of word lines each associated with a row address and a count value. A targeted refresh queue stores the highest count values and their row addresses as an ordered list. For example the list may be sorted from highest count value to lowest count value. During a targeted refresh operation, the row address at a top of the queue is used for refresh operations and removed from the queue. When a row and count value are added to the queue, the queue is re-sorted.

Abstract: Apparatuses and methods per row activation counter testing (PRACT). A memory includes an aggressor detector circuit, which determines a row address to be an aggressor address after the row address is accessed a number of times. In a normal mode the address is an aggressor after a first number of activations, while in a PRACT mode the address is an aggressor after a second (generally lower) number of activations. For example, when the row is accessed a first value may be added to a count in the normal mode and a second (generally larger) value in the PRACT mode. When the count crosses a threshold, the row is an aggressor.

Abstract: Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

Abstract: Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

Abstract: Single (1 T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

Abstract: Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

Abstract: There are provided systems and methods that include at least one memory that has a plurality of memory cells. The cells may be disposed in rows and columns. The device can further include a controller that is communicatively coupled to the at least one memory, and the controller may be configured by its hardware topology and its instruction set and/or by a communicatively coupled processor or higher level system or subsystem to maintain data integrity in the at least one memory and/or to prevent or mitigate malicious access patterns that may compromise the at least one memory. The controller may be configured to execute a deterministic protocol in conjunction with or sequentially to a probabilistic protocol to achieve one or more of the above-noted functions.

Abstract: An ear cup housing has several reference microphones, an error microphone and a speaker. A processor drives the speaker for acoustic noise cancellation and transparency, by processing the microphone signals, and performs an oversight process by adjusting the reference microphone signals in response to detecting wind noise events and scratch events. In another aspect, the ear cup housing has an outside face that is joined to an inside face by a perimeter and the reference microphones are on the perimeter. Other aspects are also described and claimed.

Abstract: An apparatus can include memory devices and a memory controller coupled to the memory devices via memory channels. The memory channels can disable a first memory channel associated with a first memory die in a respective memory chip of a memory device and perform a memory operation via a second memory channel involving a second memory die in the respective memory chip.

Abstract: Apparatuses and techniques for implementing usage-based-disturbance alert signaling are described. The technology allows usage-based-disturbance (UBD) alerts to be externally communicated from a memory device without a dedicated external interface. Rather, UBD alerts are combined with memory error/alert signals and communicated on a shared alert-related interface. UBD tracking occurs at the memory bank level, with corresponding independent UBD alert signals. These signals are efficiently combined to generate an overall UBD alert. A temporary backoff signal is generated when an overall UBD alert is sent. The backoff signal ensures requisite external timing parameters are met while allowing the individual memory banks to generate persistent UBD alerts.

Abstract: Embodiments of this application relate to the field of antennas, and provide a terminal antenna. The terminal antenna includes n radiators. The n radiators include a first radiator, a second radiator, and a third radiator. Lengths of the first radiator, the second radiator, and the third radiator form a descending arithmetic progression. The first radiator, the second radiator, and the third radiator are arranged in sequence to form two gaps. A coupling capacitance formed by the first radiator and the second radiator through the corresponding gap is greater than a coupling capacitance formed by the second radiator and the third radiator through the corresponding gap. The first radiator, the second radiator, and the third radiator are any three of the n radiators distributed in sequence.

Abstract: Methods and devices for transmitting and receiving a random access response and a communication system. The device for transmitting includes: a first transmitting unit configured to transmit a first message (MsgA) of a two-step random access procedure to a network device; wherein the first message (MsgA) comprises preambles and physical uplink shared channel (PUSCH) data; and a first monitoring unit configured to monitor in a first random access response reception time window, a physical downlink control channel (PDCCH) scheduling a first random access response (MsgB) in a two-step random access procedure transmitted by the network device; wherein the first random access response MsgB at least contains a C-RNTI and contention resolution information allocated for the terminal equipment.

Abstract: An integrated access and backhaul IAB donor-CU device, which is an F1-terminating donor-CU device of a migrating IAB node, includes: a transmitter configured to transmit IP address configuration information of an F1-terminating topology domain allocated for the migrating IAB node to a non-F1-terminating donor-CU; wherein IP address configuration information of the F1-terminating topology domain includes a TNL (transport network layer) address anchored at a donor-DU in the F1-terminating donor-CU topology for the migrating IAB node, and a receiver configured to receive IP address configuration information of the non-F1-terminating topology domain allocated for the migrating IAB node transmitted by the non-F1-terminating donor-CU; wherein IP address configuration information of the non-F1-terminating topology domain includes a new TNL address anchored at a donor-DU in the non-F1-terminating donor-CU topology for the migrating IAB node.

Abstract: Provided herein are bispecific antibodies binding to VEGF and EGFR or VEGF and HER2, and their use in treating cancer.