Abstract: Apparatuses and techniques for handling faulty usage-based-disturbance data are described. In an example aspect, a memory device uses a report flag to indicate that an address of a row that corresponds to the faulty usage-based-disturbance data is logged at a global-bank level and is accessible by a host device. The report flag also enables the memory device to avoid reporting another error until the host device has cleared information associated with a previously-reported error. In another example aspect, the memory device temporarily prevents usage-based-disturbance mitigation from being performed based on the faulty usage-based-disturbance data. This means that if the faulty usage-based-disturbance data would otherwise trigger refreshing of one or more rows that are proximate to the row corresponding to the faulty usage-based-disturbance data, the memory device does not perform these refresh operations.

Abstract: Apparatuses and techniques for logging a memory address associated with faulty usage-based disturbance data are described. In an example aspect, a memory device can detect, at a local-bank level, a fault associated with usage-based disturbance data. This detection enables the memory device to log a row address associated with the faulty usage-based disturbance data. To avoid increasing a complexity and/or a size of the memory device, some implementations of the memory device can perform the address logging at the multi-bank level with the assistance of an engine, such as a test engine. The memory device stores the logged address in at least one mode register to communicate the fault to a memory controller. With the logged address, the memory controller can initiate a repair procedure to fix the faulty usage-based disturbance data.

Abstract: A random access apparatus, applicable to a terminal equipment, includes first processor circuitry, wherein the first processor circuitry is configured to determine a random access type according to configuration information of a bandwidth part (BWP) for random access selected by the terminal equipment and downlink reference signal received power measured by the terminal equipment, perform selection of random access resources, and transmit an initial message of random access on the random access resources.

Abstract: Apparatuses and methods per row activation counter testing (PRACT). A memory includes an aggressor detector circuit, which determines a row address to be an aggressor address after the row address is accessed a number of times. In a normal mode the address is an aggressor after a first number of activations, while in a PRACT mode the address is an aggressor after a second (generally lower) number of activations. For example, when the row is accessed a first value may be added to a count in the normal mode and a second (generally larger) value in the PRACT mode. When the count crosses a threshold, the row is an aggressor.

Abstract: Provided are a display panel and a display device. An array layer is located on a substrate. A display layer is located on a side of the array layer facing away from the substrate and includes light-emitting elements. A color filter layer is located on a side of the display layer facing away from the array layer. The color filter layer includes a light-blocking layer and color filters. The light-blocking layer includes first light-blocking part. At least one light-transmitting aperture is disposed in the first light-blocking part. First metal part overlaps the first light-blocking part. Further provided is a display device including the preceding display panel.

Abstract: Disclosed is a brand value evaluation method, comprising: acquiring a brand set to be processed containing a plurality of brands to be processed; collecting evaluation data corresponding to the brand set to be processed, and identifying the brand set to be processed based on the evaluation data to obtain a reputation degree and a volume of each brand to be processed in the brand set to be processed; acquiring a brand to be evaluated, and judging whether the brand to be evaluated exists in the brand set to be processed; when it exists, determining the reputation degree and volume of the brand to be evaluated as a target reputation degree and a target volume; determining a value for the brand to be evaluated according to the reputation degree of each brand to be processed, the volume of each brand to be processed, the target reputation degree and the target volume.

Abstract: Apparatuses and methods for per-row count based refresh target identification with sorting. A memory includes a number of word lines each associated with a row address and a count value. A targeted refresh queue stores the highest count values and their row addresses as an ordered list. For example the list may be sorted from highest count value to lowest count value. During a targeted refresh operation, the row address at a top of the queue is used for refresh operations and removed from the queue. When a row and count value are added to the queue, the queue is re-sorted.

Abstract: A circuit breaker that includes a circuit breaker housing, a button mechanism arranged inside the circuit breaker housing, an operating mechanism connected with the button mechanism, a movable contact connected with the operating mechanism, a static contact co-operated with the movable contact, the button mechanism being operable to enable the circuit breaker to switch on/switch off by means of the operating mechanism; the circuit breaker also includes an electric mechanism arranged inside the circuit breaker housing, the electric mechanism is drivingly co-operated with the button mechanism or the operating mechanism, the electric mechanism can actuate the circuit breaker to switch on/switch off by means of the operating mechanism, or the electric mechanism can actuate the circuit breaker to switch on/switch off by means of the cooperation of the button mechanism.

Abstract: Disclosed are an isolation method for a high-performance computer system, and a high-performance computer system. The isolation method comprises node-level isolation performed. The node-level isolation comprises: configuring a routing table for each computing node, and configuring, in the routing table, valid routing information for computing node pairs; when any one source computing node needs to communicate with a target computing node, determining, by lookup, whether valid routing information exists between the source computing node and the target computing node according to the configured routing table; if so, allowing the source computing node to communicate with the target computing node; otherwise, forbidding the source computing node from communicating with the target computing node.

Abstract: Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

Abstract: Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

Abstract: Single (1 T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

Abstract: Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

Abstract: There are provided systems and methods that include at least one memory that has a plurality of memory cells. The cells may be disposed in rows and columns. The device can further include a controller that is communicatively coupled to the at least one memory, and the controller may be configured by its hardware topology and its instruction set and/or by a communicatively coupled processor or higher level system or subsystem to maintain data integrity in the at least one memory and/or to prevent or mitigate malicious access patterns that may compromise the at least one memory. The controller may be configured to execute a deterministic protocol in conjunction with or sequentially to a probabilistic protocol to achieve one or more of the above-noted functions.

Abstract: An ear cup housing has several reference microphones, an error microphone and a speaker. A processor drives the speaker for acoustic noise cancellation and transparency, by processing the microphone signals, and performs an oversight process by adjusting the reference microphone signals in response to detecting wind noise events and scratch events. In another aspect, the ear cup housing has an outside face that is joined to an inside face by a perimeter and the reference microphones are on the perimeter. Other aspects are also described and claimed.

Abstract: An apparatus can include memory devices and a memory controller coupled to the memory devices via memory channels. The memory channels can disable a first memory channel associated with a first memory die in a respective memory chip of a memory device and perform a memory operation via a second memory channel involving a second memory die in the respective memory chip.

Abstract: A method is provided for forming an integrated circuit (IC) chip package structure. The method includes: providing an interposer having a front surface and a back surface, the interposer comprising a substrate, at least one routing region, and at least one non-routing region; forming at least one warpage-reducing trench in the at least one non-routing region, wherein the at least one warpage-reducing trench extends from the front surface of the interposer to a first depth, the first depth smaller than a thickness between the front surface and the back surface of the interposer; depositing a warpage-relief material in the at least one warpage-reducing trench; and bonding the group of IC dies to the front surface of the interposer.

Abstract: A wireless communication method for use in a wireless terminal is disclosed. The wireless communication method comprises receiving, from the wireless network node, a second signal based on a quasi-co-location assumption of a first signal when at least one event occurs, wherein the first signal and the second signal overlap in at least one time unit.

Abstract: The present disclosure relates to a method for predicting an amount of water-sealed gas in a high-sulfur water-bearing gas reservoir. The method solves the problem that no method has yet been proposed for predicting the amount of water-sealed gas in a high-sulfur water-bearing gas reservoir. According to the technical solution, the method includes: considering that the volume of the gas reservoir does not change during the production of the constant-volume gas reservoir, deriving, based on a material balance method, a material balance equation of the high-sulfur water-bearing gas reservoir in consideration of water-sealed gas and water-soluble gas, solving and drawing a chart of water-sealed gas in the high-sulfur water-bearing gas reservoir by an iterative algorithm, obtaining a recovery factor of the high-sulfur water-bearing gas reservoir in consideration of water-sealed gas and water-soluble gas, and further obtaining the amount of water-seal gas in the high-sulfur water-bearing gas reservoir.

Abstract: Apparatuses and techniques for implementing usage-based-disturbance alert signaling are described. The technology allows usage-based-disturbance (UBD) alerts to be externally communicated from a memory device without a dedicated external interface. Rather, UBD alerts are combined with memory error/alert signals and communicated on a shared alert-related interface. UBD tracking occurs at the memory bank level, with corresponding independent UBD alert signals. These signals are efficiently combined to generate an overall UBD alert. A temporary backoff signal is generated when an overall UBD alert is sent. The backoff signal ensures requisite external timing parameters are met while allowing the individual memory banks to generate persistent UBD alerts.