Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for managing sPPR undo operations based on activation count values of original rows after a repair. After packaging, it may be necessary to perform post-package repair operations on rows of the memory. During an sPPR operation, an address of an original row of memory may be associated with an open repair address instead, such as when the original row is determined to be damaged or defective. The sPPR repair may be reversed by performing an sPPR undo operation. While the repair row is associated with the original row, the activation count of the original row may become corrupted, and it may be necessary to reset the activation count associated with the original row during a repair undo operation to prevent unnecessary refresh operations occurring on the original row and adjacent rows.

Abstract: Apparatuses and techniques for implementing usage-based-disturbance alert signaling are described. The technology allows usage-based-disturbance (UBD) alerts to be externally communicated from a memory device without a dedicated external interface. Rather, UBD alerts are combined with memory error/alert signals and communicated on a shared alert-related interface. UBD tracking occurs at the memory bank level, with corresponding independent UBD alert signals. These signals are efficiently combined to generate an overall UBD alert. A temporary backoff signal is generated when an overall UBD alert is sent. The backoff signal ensures requisite external timing parameters are met while allowing the individual memory banks to generate persistent UBD alerts.

Abstract: A value associated with a number of accesses of a word line and a length of said accesses may be stored on said word line. A timer may provide a periodic signal that increments a counter to update the value. The updated value may then be written back to the word line. In some examples, a memory device including the word lines may have a specification that prevents the word line from closing prior to writing the updated value to the word line.

Abstract: Apparatuses and methods per-row count based refresh target identification. A memory device stores count values associated with the word lines. An aggressor detector circuit stores a maximum of the count values and a row address associated with the maximum count value. Responsive to a targeted refresh signal, the stored count value is compared to a threshold. If the count value has crossed the threshold, then a targeted refresh operation may be performed on one or more refresh addresses based on the stored address, and the count value may be reset.

Abstract: Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

Abstract: This application provides a cavity antenna and an electronic device. The cavity antenna includes a metal backplane, a dielectric substrate, and a flexible printed circuit board. The dielectric substrate is located between the flexible printed circuit board and the metal backplane. The flexible printed circuit board is electrically connected to the metal backplane. The flexible printed circuit board includes a body part and a bending plate. The body part is provided with an avoidance hole. The avoidance hole is spaced apart from a peripheral surface of the body part. The bending plate is fixedly connected to a hole wall of the avoidance hole and is bendable relative to the body part. When the bending plate is bent relative to the body part, the bending plate is electrically connected to the metal backplane.

Abstract: Apparatuses and techniques for enabling efficient usage-based-disturbance (UBD) mitigation are described. Mitigating the adverse effects of UBD can entail tracking a quantity of accesses to memory rows using activation counts. Generally, the activation count of a particular row can be reset to zero based on memory refresh operations applied to the particular row and proximate rows thereof. The multiple storage bits for the UBD data consume chip area, and manipulating the storage bits consumes power. Described implementations increase the effective quantity of UBD data bits without increasing chip area. By the strategic placement of a refresh flag in proximity to certain bits of the activation count, power can be saved when manipulating the UBD data in response to a refresh operation by asserting the relevant column select circuitry. Further, enhancing the evaluation of a refresh boundary can facilitate updating the activation count during memory access read and write operations.

Abstract: Apparatuses and methods aggressor queue mitigation based threshold. A memory device detects aggressor rows by changing a count value associated with the row when it is accessed and comparing the count value to a mitigation threshold. Identified aggressor rows are stored in an aggressor queue. The value of the mitigation threshold is set based on a number of addresses which are stored in the aggressor queue. For example the threshold may increase as the number of addresses in the queue increases.

Abstract: Systems, methods, and apparatus for memory device security and row hammer mitigation are described. A control mechanism may be implemented in a front-end and/or a back-end of a memory sub-system to refresh rows of the memory. A row activation command having a row address at control circuitry of a memory sub-system and incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system may be received. Control circuitry may determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count may be incremented each time the CAM is full. A refresh command to the row address may be issued when a determination is made that the first count is greater than the RHT minus the second count.

Abstract: The present disclosure provides systems and methods for assessing a mental state of a subject in a single session or over multiple different sessions, using for example an automated module to present and/or formulate at least one query based in part on one or more target mental states to be assessed. The query may be configured to elicit at least one response from the subject. The query may be transmitted in an audio, visual, and/or textual format to the subject to elicit the response. Data comprising the response from the subject can be received. The data can be processed using one or more individual, joint, or fused models. One or more assessments of the mental state associated with the subject can be generated for the single session, for each of the multiple different sessions, or upon completion of one or more sessions of the multiple different sessions.

Abstract: Methods, systems, and devices for power stabilization for memory systems are described. A memory system may be implemented with a power source that is configured to adjust one or more aspects of its regulation based on an indication associated with a power consumption for one or more operations to be performed by the memory system. For example, a memory system may include a controller configured to determine the power consumption for performing upcoming operations (e.g., based on the quantity of operations and the type of operations), and transmit an indication associated with the power consumption to the power source (e.g., as a proactive or feed-forward control indication). The power source may adjust its regulation based on the indication from the controller, which may include adjusting gains, circuitry, or other regulation configurations or characteristics associated with providing the power for performing the upcoming operations (e.g., at a regulated voltage).

Abstract: Apparatuses and techniques for efficient handling of data errors and usage-based disturbances are described. To enable efficient utilization of time-limited resources, a memory device includes control circuitry that performs multiple different types of operations responsive to “confiscating” a refresh-pump time interval. The memory device is responsible for performing various functionalities internally while reducing the impact such functionalities may have on servicing memory requests from an external entity. Accordingly, a memory device may confiscate refresh-pump opportunities and instead perform other operations. To efficiently utilize a refresh-pump opportunity, the control circuitry can perform an error-handling operation on a codeword stored in a first bank and perform a usage-based disturbance mitigation operation on a row in a second bank during the confiscated time interval. Further, the usage-based disturbance mitigation operation can be performed across multiple banks except for the first bank.

Abstract: A method for providing roaming radio access at a first Public Land Mobile Network, PLMN. An indicator is broadcast from a radio access node of the first PLMN, the indicator indicating that the access node will provide connectivity service to subscribers of a second, different PLMN, despite the subscribers of the second PLMN having a forbidden PLMN list that includes the first PLMN.

Abstract: Apparatuses and techniques for implementing mixed-array dynamic random-access memory (DRAM) architecture are described. Processors demand ever faster memories. To meet this demand, DRAM is manufactured with increasing quantities of memory banks. This approach adds area and processing overhead, which translates to increased cost and power usage. This document describes a memory die having a DRAM array with first and second portions that store normal data using memory cells with first and second properties. A first performance property of the first portion is higher than a second performance property of the second portion. Also, a first cost property of the first portion may be higher than a second cost property of the second portion. This mixed-array approach enables some data to be accessed at a higher performance level without resorting to increasing the quantity of memory banks. In some cases, a third portion stores usage-based-disturbance data at a higher performance level.

Abstract: Various embodiments are directed to an elevator positioning system, comprising: a transceiver disposed within an elevator shaft; a first positioning element; a second positioning element; and a controller communicably coupled to the transceiver, wherein the controller is configured to: determine a first distance between the transceiver and the first positioning element; determine a calibration distance between the transceiver and the second positioning element based at least in part on a second reflection detected by the transceiver from the second positioning element at a first instance; based at least in part on the first distance and the calibration distance, calculate an adjusted elevator car position defined at least in part by a shaft displacement compensation distance; and cause an elevator car to move about a vertical axis of the elevator shaft to a vertical position within the elevator shaft that corresponds at least in part to the adjusted elevator car position.

Abstract: A cellular network mobile station (MS) is configured for roaming operation. A prioritization of one or more Public Land Mobile Network (PLMN) configurations is stored at the MS. When the MS is attached or registered for access to a PLMN that is not a Home PLMN or PLMN configuration that is not a highest priority PLMN configuration, it performs an idle mode search for a higher priority PLMN configuration at intervals of time. A duration of the intervals is determined according to a primary search period parameter stored at the MS. The MS is configured with a secondary search period parameter, which indicates one or more factors to be applied to the primary search period parameter when determining the duration of the intervals, such that each of the factors is applied according to a respective associated condition indicative of a number of PLMN configurations available for the MS to access.

Abstract: Apparatuses and techniques for implementing refresh latency indication for refresh operations are described. A memory system may separate memory dies into different ranks. Sending separate refresh commands to each rank congests the command bus. Sending a common refresh command to multiple ranks, on the other hand, causes a large current spike as many dies initiate the refresh operation at the same time. To efficiently prevent the large current spike and thereby lower the costs of a power delivery network, different dies can delay initiation of the refresh commands by different amounts. To do so, a host device can program different dies with different refresh latency indications, which determine lengths of each delay period before starting the refresh operation. The dies can also operate based on an enablement indication that enables the refresh latency mechanism. Staggering the start times of refresh operations can also control current spikes without regard to ranks.

Abstract: Apparatuses and techniques for reporting a notification-type event are described. In an example aspect, a memory device includes a dedicated notification pin for reporting one or more notification-type events to a memory controller. Through the notification pin, the memory device can indicate an occurrence of various notification-type events, one or more of which can be associated with mitigating usage-based disturbance. In contrast to an alert pin, the notification pin enables an operation of the memory controller to continue uninterrupted. In other words, notification-type events that are reported via the notification pin do not need to interrupt an operation of the memory controller. In this way, the notification pin can be used to communicate notifications without degrading performance of the memory controller. Also, with a dedicated notification pin, the memory controller can avoid continuously polling mode registers of the memory device for information, thereby conserving power and temporal resources.

Abstract: An apparatus for transmitting and receiving signals, applicable to a first integrated access and backhaul node donor central unit (IAB-donor-CU) includes a first controller configured to: transmit a traffic offload request to a second TAB-donor-CU; and receive a reply of agreement of traffic offload or a reply of rejection of traffic offload transmitted by the second TAB-donor-CU.

Abstract: Apparatuses and techniques for implementing self-refresh status indications for self-refresh exit are described. To save power, a memory device can control refresh operations, but the memory device is typically unavailable in this self-refresh mode. During self-refresh exiting, the memory device typically remains unavailable for normal array access operations while concluding any refresh operations that are already in progress. Portions of the memory array, however, are usually not performing a refresh operation. To enable a host device to perform read and write operations on these available portions during the self-refresh exit time, the memory device provides an indication of a self-refresh status in example implementations. The indication can be a Boolean variable that pertains to an entire array. Alternatively, the indication can include multiple bits that respectively correspond to multiple portions, such as memory banks or bank groups. In this way, the host device can return to normal operations sooner.