Abstract: Embodiments of the present disclosure provide an array substrate and manufacturing method thereof, and a display device, the array substrate includes: a base substrate, a thin film transistor group, and a signal shielding structure. The thin film transistor group includes first and second thin film transistors overlapped with each other in a first direction perpendicular to a main surface of the base substrate; the first thin film transistor includes a first active layer and a first gate electrode, and the second thin film transistor includes a second active layer and a second gate electrode. The signal shielding structure is located between the first and second thin film transistors, wherein an orthographic projection of the first gate electrode on the base substrate is within a range of an orthographic projection of the signal shielding structure on the base substrate.

Abstract: A display substrate includes an anode material layer extending at least partially across multiple subpixels. The anode material layer includes a first anode portion at least partially in subpixel regions and a second anode portion at least partially in an inter-subpixel region. The first anode portion includes a doped anode impurity. The first anode portion and the second anode portion include at least one material in common. A weight percentage of the doped anode impurity in the first anode portion is higher than a weight percentage of the doped anode impurity in the second portion. A weight ratio of the doped anode impurity to the at least one material in common in the first anode portion is higher than a weight ratio of the doped anode impurity to the at least one material in common in the second anode portion. The second anode portion spaces apart adjacent subpixels.

Abstract: A display substrate is provided. The display substrate includes a plurality of functional material layers extending at least partially across multiple subpixels. The plurality of functional material layers include a first portion in an inter-subpixel region, and a second portion in subpixel regions. The first portion includes a doped impurity. The first portion and the second portion include at least one functional material in common. A weight percentage of the doped impurity in the first portion is higher than a weight percentage of the doped impurity in the second portion. The first portion spaces apart adjacent subpixels. The second portion includes a light emitting layer of a respective subpixel.

Abstract: A reconstruction method of an Emission Computed Tomography image, an apparatus, a device, and a storage medium are provided in the present disclosure. The method includes: acquiring a first ECT image sequence, inputting the first ECT image sequence into a trained intermediate frame prediction network to obtain an estimated second ECT image sequence, and reconstructing a target second ECT image sequence based on the estimated second ECT image sequence serving as a prior image. Temporal resolutions of both the target second ECT image sequence and the estimated second ECT image sequence are higher than that of the first ECT image sequence.

Abstract: A display substrate and preparation method therefor, and display apparatus. The display substrate includes multiple circuit units, a circuit unit includes a pixel drive circuit, a first scan signal line, a second scan signal line, a third scan signal line and a light emitting signal line. The pixel drive circuit at least includes an eighth transistor and a ninth transistor. An orthographic projection of first scan signal line on a plane of the display substrate at least partially overlaps that of second scan signal line on the plane of the display substrate, an orthographic projection of third scan signal line on the plane of the display substrate at least partially overlaps that of light emitting signal line on plane of the display substrate, an orthographic projection of eighth transistor on the plane of the display substrate at least partially overlaps that of ninth transistor on plane of the display substrate.

Abstract: A driving backplane includes a first substrate, a thick copper layer, a second substrate, and a driving layer stacked in sequence. The thick copper layer is provided with a driving wire configured to load a driving signal. The driving layer is provided with a driving circuit. The driving circuit is electrically connected to the driving wire through a via.

Abstract: An emission tomography image processing method includes: acquiring local medical images of a target object, where different local medical images correspond to different spatial positions or different tissue regions; predicting noise level information corresponding to the local medical images; and performing, based on the noise level information corresponding to the local medical images, image denoising on the local medical images to obtain a target medical image, where at least two of the local medical images correspond to different noise level information.

Abstract: The present disclosure relates to a method for identifying a prompt-y event, which includes: obtaining first time-of-flight (TOF) data of multiple double coincidence events detected by a detector device; determining second TOF data of one or more triple coincidence events based on the first TOF data, performing verification operations on the second TOF data of the triple coincidence events to determine a prompt-? event in each of the triple coincidence events. The embodiments of this application can effectively identify prompt gamma photon events by using TOF data, which is helpful for separating dual-nuclide signals.

Abstract: The present disclosure discloses an image special effect processing method and apparatus, an electronic device and a computer-readable storage medium. The method includes: in response to an instruction for adding a special effect object on an initial image, determining a target display region of the special effect object on the initial image, where the target display region is a foreground region or a background region of the initial image, the foreground region is an image region where a target object is located in the initial image, and the background region is an image region other than the foreground region in the initial image; and displaying a part of the special effect object located in the target display region on the initial image to obtain a target image.

Abstract: A system and a method for medical image processing are provided. The method includes: obtaining a first medical image; obtaining a trained image perception restoration model; the trained image perception restoration model includes an image quality perception sub-model and an image restoration sub-model; and inputting the first medical image into the trained image perception restoration model to obtain a second medical image. The image quality perception sub-model is configured to determine either or both of a first quality evaluation value of the first medical image and a second quality evaluation value of the second medical image, the image restoration sub-model is configured to determine the second medical image, and the quality of the second medical image is higher than that of the first medical image.

Abstract: Disclosed in this disclosure are a pad, lead frame, and sensor packaging structure for attenuating an eddy current effect, which are applied to the field of semiconductor preparation. The pad includes a first pad component and a second pad component, where the first pad component and the second pad component are disposed on two adjacent sides of a chip placement region; and the first pad component and the second pad component are electrically connected, such that the first pad component and the second pad component surround the chip placement region on the two adjacent sides. In this disclosure, by means of arranging the pad along two adjacent sides of a chip, the formation of closed eddy current loops in a metal frame can be further reduced, thereby weakening the impact of a reversed magnetic field, and thus improving the detection sensitivity and accuracy of a sensor.

Abstract: A lead-wire frame structure for packaging and a sensor package structure, which are applied to the field of sensor preparation. The lead-wire frame structure comprises: a bonding-pad component and a plurality of pin components, wherein the bonding-pad component is provided with an inward recess in a plane direction of a coplane which is formed by the bonding-pad component and the plurality of pin components. In the plane direction, arc-shaped packaging interfaces for offsetting stresses are formed in an aligned manner on an inner contour of the recess and an outer contour of the recess in the bonding-pad component. In the present application, the bonding-pad component is provided with the inward recess in the plane direction, and the aligned packaging interfaces of the inner contour of the recess and the outer contour of the recess arc designed to be of arc-shaped structures, which can offset internal and external stresses.

Abstract: The present disclosure provides video effect packet generation method and apparatus, device, and storage medium. The method of generating the video effects package includes: obtaining an effects control with an empty input in a general effects graph, and determining the effects control as a target effects control; obtaining effects information in the target effects control and switching to a script effects graph; creating, in the script effects graph and according to the creation operation triggered by the user, a getting control, a frame capture control, a selection control and a setting control, the getting control and the setting control corresponding to the effects information; connecting the getting control, the frame capture control, the selection control and the setting control in sequence to input the captured video frames to the target effects control to generate a video effects package.

Abstract: A packaged chip and a current sensor, which are applied to the field of chip packaging. The packaged chip comprises: a substrate, a protective layer made of the same material as the substrate, and an active region prepared on one side surface of the substrate, wherein the side of the active region facing away from the substrate is bonded to the protective layer; and an isolation structure is formed between the protective layer and the substrate and on a side face of the active region. By means of the present application, the side, facing away from a substrate, of an active region prepared on the substrate is connected to a protective layer, and an isolation structure is formed between the protective layer and the substrate and on a side face of the active region, such that insulated isolation for the active region is formed.

Abstract: The embodiments relate to the field of terminals, and provide a processing method for a virtual display and an electronic device. The method includes: communicating with an application process by using a communication thread in an image processing process when the image processing process performs graphic interface (GI) composition of a first frame, to obtain a communication result; and sending a composite GI to the virtual display created by the application process when the communication result is normal, and deleting a virtual display object when the communication result is abnormal. In this case, a task thread of the image processing process is prevented from being blocked when the application process does not respond in time or the communication with the image processing process is abnormal, so that impact from the abnormality is controlled in the communication thread without spreading to other task threads.

Abstract: Disclosed are a rubber asphalt-derived volatile organic compounds (VOCs) inhibitor based on a metal organic frameworks (MOFs) material and a preparation method thereof, and a smoke-suppression rubber asphalt and a preparation method thereof. The inhibitor has a chemical formula of CxHyO32Zr6, where x is in a range of 48 to 120, and y is in a range of 28 to 76; and the inhibitor is a zirconium-based MOFs material having a cubic crystal structure with a crystal pore size of 0.5 nm to 2 nm and a specific surface area of 1,000 m2/g to 3,200 m2/g.

Abstract: A thin film transistor includes a substrate and an active layer having a channel region. The active layer includes a first active pattern and at least one second active pattern. The first active pattern includes a bottom surface, a top surface and at least one side surface. The at least one side surface connects the bottom and top surfaces, and is in contact with the at least one second active pattern. A length direction of each side surface is approximately perpendicular to a length direction of the channel region. A material of at least the top surface of the first active pattern includes a first polysilicon material, and a material of the second active pattern includes a second polysilicon material; and in the length direction of the channel region, an average grain size of the first polysilicon material is greater than an average grain size of the second polysilicon material.

Abstract: A high-voltage sampling circuit includes a high-voltage MOS transistor and a battery sampling device. An output terminal of the battery sampling device is connected to a gate of the high-voltage MOS transistor and is configured to output a high or low level; an analog-to-digital conversion terminal thereof is connected to a source of the high-voltage MOS transistor and is configured to collect a voltage at the source of the high-voltage MOS transistor. A drain of the high-voltage MOS transistor is connected to the positive electrode of the battery pack through a first voltage-dividing resistor, and the source thereof is connected to the negative electrode of the battery pack through a second voltage-dividing resistor. The battery sampling device is configured to, when outputting a high level to the high-voltage MOS transistor, collect the voltage passing through the MOS transistor and convert the voltage to obtain a supply voltage of the battery pack.

Abstract: Various embodiments include methods and devices for identifying core threads of a program executing by a processor. Some embodiments may include hooking an event by a kernel interface, calculating a total time cost for executing a thread of the program based on hooking the event by the kernel interface, returning the total time cost for executing the thread and a thread identifier of the thread to a core thread identifier program by the kernel, and determining a core thread of the program based on the total time cost for executing the thread and the thread identifier of the thread by the core thread identifier program.