Patents by Inventor Yang Pan

Yang Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12278125
    Abstract: Methods for making thin-films on semiconductor substrates, which may be patterned using EUV, include: depositing the organometallic polymer-like material onto the surface of the semiconductor substrate, exposing the surface to EUV to form a pattern, and developing the pattern for later transfer to underlying layers. The depositing operations may be performed by chemical vapor deposition (CVD), atomic layer deposition (ALD), and ALD with a CVD component, such as a discontinuous, ALD-like process in which metal precursors and counter-reactants are separated in either time or space.
    Type: Grant
    Filed: October 5, 2023
    Date of Patent: April 15, 2025
    Assignee: Lam Research Corporation
    Inventors: Jengyi Yu, Samantha S. H. Tan, Mohammed Haroon Alvi, Richard Wise, Yang Pan, Richard Alan Gottscho, Adrien Lavoie, Sivananda Krishnan Kanakasabapathy, Timothy William Weidman, Qinghuang Lin, Jerome S. Hubacek
  • Patent number: 12266573
    Abstract: In an embodiment, a device includes: an isolation region on a substrate; a first semiconductor fin protruding above the isolation region; a second semiconductor fin protruding above the isolation region; and a dielectric fin between the first semiconductor fin and the second semiconductor fin, the dielectric fin protruding above the isolation region, the dielectric fin including: a first layer including a first dielectric material having a first carbon concentration; and a second layer on the first layer, the second layer including a second dielectric material having a second carbon concentration, the second carbon concentration greater than the first carbon concentration.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi Chen Ho, Yiting Chang, Chi-Hsun Lin, Zheng-Yang Pan
  • Patent number: 12266542
    Abstract: A method for atomic layer etching a metal containing layer is provided. At least a region of a surface of the metal containing layer is modified to form a modified metal containing region by exposing a surface of the metal containing layer to a modification gas, wherein adjacent to the modified metal containing region remains an unmodified metal containing region. The modified metal containing region is selectively removed with respect to the unmodified metal containing region by exposing the surface of the metal containing layer to an inert bombardment plasma generated from an inert gas.
    Type: Grant
    Filed: February 7, 2024
    Date of Patent: April 1, 2025
    Assignee: Lam Research Corpporation
    Inventors: Wenbing Yang, Mohand Brouri, Samantha SiamHwa Tan, Shih-Ked Lee, Yiwen Fan, Wook Choi, Tamal Mukherjee, Ran Lin, Yang Pan
  • Publication number: 20250098259
    Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The method includes forming a first fin structure and a second fin structure from a substrate, depositing a first conformal layer over the first and second fin structures and between the first and second fin structures, depositing a second conformal layer on the first conformal layer, depositing a third conformal layer on the second conformal layer, depositing a fourth conformal layer on the third conformal layer, depositing a first insulating material on the fourth conformal layer between the first and second fin structures, and depositing a second insulating material on the first insulating material. The first and second fin structures are embedded by the second insulating material. The method further includes removing portions of the second insulating material and the first, second, third, and fourth conformal layers to expose the first and second fin structures.
    Type: Application
    Filed: September 14, 2023
    Publication date: March 20, 2025
    Inventors: Ya-Wen CHIU, Yi-Hua CHENG, Szu-Ying CHEN, Zheng-Yang PAN
  • Patent number: 12256645
    Abstract: A method is provided. A substrate situated in a chamber is exposed to a halogen-containing gas comprising an element selected from the group consisting of silicon, germanium, carbon, titanium, and tin, and igniting a plasma to modify a surface of the substrate and form a modified surface. The substrate is exposed to an activated activation gas to etch at least part of the modified surface.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: March 18, 2025
    Assignee: Lam Research Corporation
    Inventors: Wenbing Yang, Tamal Mukherjee, Zhongwei Zhu, Samantha SiamHwa Tan, Ran Lin, Yang Pan, Ziad El Otell, Yiwen Fan
  • Publication number: 20250087498
    Abstract: Tin oxide films are used as mandrels in semiconductor device manufacturing. In one implementation the process starts by patterning a tin oxide layer using at least one of a hydrogen-based etch chemistry and a chlorine-based etch chemistry, and using patterned photoresist as a mask, thereby providing a substrate having a plurality of protruding tin oxide features (mandrels). Next, a conformal layer of spacer material is formed both on the horizontal surfaces and on the sidewalls of the mandrels. The spacer material is then removed from the horizontal surfaces exposing the tin oxide material of the mandrels, without fully removing the spacer material residing at the sidewalls of the mandrels. Next, mandrels are selectively removed (e.g., using hydrogen-based etch chemistry), while leaving the spacer material that resided at the sidewalls of the mandrels. The resulting spacers can be used for patterning underlying layers on the substrate.
    Type: Application
    Filed: November 22, 2024
    Publication date: March 13, 2025
    Inventors: Jengyi Yu, Samantha S.H. Tan, Seongjun Heo, Boris Volosskiy, Sivananda Krishnan Kanakasabapathy, Richard Wise, Yang Pan, Hui-Jung Wu
  • Publication number: 20250081549
    Abstract: Various embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a plurality of semiconductor layers vertically stacked, a plurality of inner spacers, each being disposed between two adjacent semiconductor layers. The structure also includes a source/drain feature in contact with each of the inner spacers, a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers, and a cap layer disposed between the source/drain feature and each of the plurality of the semiconductor layers.
    Type: Application
    Filed: August 30, 2023
    Publication date: March 6, 2025
    Inventors: Yu-Yu Chen, Zheng-Yang Pan, Ya-Wen Chiu
  • Publication number: 20250077063
    Abstract: The embodiments of the disclosure provide a method for activating a system function, a host, and a computer readable storage medium. The method includes: providing a visual content; tracking a first motion state of a physical object by using a tracking device; and in response to determining that the first motion state of the physical object indicates that a distance between the physical object and the host is less than a first distance threshold and the physical object corresponds to a first content region in the visual content, performing a first system function corresponding to the first content region, wherein the first content region corresponds to a first physical region on a body of the host.
    Type: Application
    Filed: March 18, 2024
    Publication date: March 6, 2025
    Applicant: HTC Corporation
    Inventors: Jing-Lung Wu, Sheng-Yang Pan
  • Publication number: 20250056870
    Abstract: Embodiments of the present disclosure provide a method for selectively forming a seed layer over semiconductor fins. Some embodiments provide forming the selective seed layer using a mono-silane at an increased temperature. Some embodiments provide depositing a hetero-crystalline silicon cap layer over the bottom-up gap layer to improve gap filling and tune profiles of fin structures.
    Type: Application
    Filed: August 11, 2023
    Publication date: February 13, 2025
    Inventors: Ya-Wen Chiu, De Jhong Liao, Yu-Yu Chen, Szu-Ying Chen, Zheng-Yang Pan
  • Publication number: 20250049940
    Abstract: A combination of an anti-TROP-2 antibody-drug conjugate and anti-PD-L1 antibody or other chemotherapeutic drugs such as Carboplatin or Cisplatin, and an application of the combination in the preparation of drugs for preventing and/or treating tumor diseases, wherein the anti-TROP-2 antibody may be Sacituzumab.
    Type: Application
    Filed: January 11, 2023
    Publication date: February 13, 2025
    Applicant: SICHUAN KELUN-BIOTECH BIOPHARMACEUTICAL CO., LTD.
    Inventors: Xiaoping JIN, Yina DIAO, Qi GUO, Gesha LIU, Lian LU, Yujun WEI, Wenguo YIN, Suxia WANG, Yang PAN, Junyou GE
  • Patent number: 12223715
    Abstract: A method, a system and a recording medium for accessory pairing are provided. The method comprises: determining a type of the accessory based on the identifying information of an accessory; recognizing a type of a user body part according to an image; in response to the accessory is applicable to the user body part according to the type of accessory and the type of the user body part, obtaining a first position of the accessory within an environment and obtaining a second position of the user body part within the environment; and configuring the accessory to pair the user body part according to the first position of the accessory and the second position of the user body part.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: February 11, 2025
    Assignee: HTC Corporation
    Inventor: Sheng-Yang Pan
  • Publication number: 20250020504
    Abstract: A printer and a printing method therefor is disclosed. The printing method includes: S1: editing a print template at a printer, the edited print template including a custom field and a variable field, and printing the custom field before the variable field; S2: obtaining weighing data at a weighing instrument; S3: obtaining weighing data that matches the variable field, inserting the matched weighing data in a position of the corresponding variable field, and printing the weighing data after the weighing data is completely matched; determining whether the weighing data at the instrument is completely sent and/or completely obtained by the printer, and if the weighing data is not completely sent and/or obtained, returning to step S2, or if the weighing data is completely sent and/or obtained, performing step S5; and S5: if there is still a custom field not printed in the print template, printing the custom field not printed.
    Type: Application
    Filed: December 5, 2022
    Publication date: January 16, 2025
    Inventors: Yongkan Ge, Yang Pan
  • Patent number: 12183589
    Abstract: Tin oxide films are used as mandrels in semiconductor device manufacturing. In one implementation the process starts by patterning a tin oxide layer using at least one of a hydrogen-based etch chemistry and a chlorine-based etch chemistry, and using patterned photoresist as a mask, thereby providing a substrate having a plurality of protruding tin oxide features (mandrels). Next, a conformal layer of spacer material is formed both on the horizontal surfaces and on the sidewalls of the mandrels. The spacer material is then removed from the horizontal surfaces exposing the tin oxide material of the mandrels, without fully removing the spacer material residing at the sidewalls of the mandrels. Next, mandrels are selectively removed (e.g., using hydrogen-based etch chemistry), while leaving the spacer material that resided at the sidewalls of the mandrels. The resulting spacers can be used for patterning underlying layers on the substrate.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: December 31, 2024
    Assignee: Lam Research Corporation
    Inventors: Jengyi Yu, Samantha S. H. Tan, Seongjun Heo, Boris Volosskiy, Sivananda Krishnan Kanakasabapathy, Richard Wise, Yang Pan, Hui-Jung Wu
  • Patent number: 12183604
    Abstract: Methods for making thin-films on semiconductor substrates, which may be patterned using EUV, include: depositing the organometallic polymer-like material onto the surface of the semiconductor substrate, exposing the surface to EUV to form a pattern, and developing the pattern for later transfer to underlying layers. The depositing operations may be performed by chemical vapor deposition (CVD), atomic layer deposition (ALD), and ALD with a CVD component, such as a discontinuous, ALD-like process in which metal precursors and counter-reactants are separated in either time or space.
    Type: Grant
    Filed: March 15, 2023
    Date of Patent: December 31, 2024
    Assignee: Lam Research Corporation
    Inventors: Jengyi Yu, Samantha S. H. Tan, Mohammed Haroon Alvi, Richard Wise, Yang Pan, Richard Alan Gottscho, Adrien LaVoie, Sivananda Krishnan Kanakasabapathy, Timothy William Weidman, Qinghuang Lin, Jerome S. Hubacek
  • Publication number: 20240429045
    Abstract: Provided herein are methods and systems for reducing roughness of an EUV resist and improving etched features. The methods involve descumming an EUV resist, filling divots of the EUV resist, and protecting EUV resists with a cap. The resulting EUV resist has smoother features and increased selectivity to an underlying layer, which improves the quality of etched features. Following etching of the underlying layer, the cap may be removed.
    Type: Application
    Filed: June 27, 2024
    Publication date: December 26, 2024
    Inventors: Jengyi Yu, Samantha S.H. Tan, Liu Yang, Chen-Wei Liang, Boris Volosskiy, Richard Wise, Yang Pan, Da Li, Ge Yuan, Andrew Liang
  • Publication number: 20240429040
    Abstract: A method for protecting a surface of a substrate during processing includes a) providing a solution forming a co-polymer having a ceiling temperature; b) dispensing the solution onto a surface of the substrate to form a sacrificial protective layer, wherein the co-polymer is kinetically trapped to allow storage at a temperature above the ceiling temperature; c) exposing the substrate to ambient conditions for a predetermined period; and d) de-polymerizing the sacrificial protective layer by using stimuli selected from a group consisting of ultraviolet (UV) light and heat.
    Type: Application
    Filed: September 6, 2024
    Publication date: December 26, 2024
    Inventors: Stephen M. SIRARD, Ratchana LIMARY, Yang PAN, Diane HYMES
  • Publication number: 20240419078
    Abstract: Development of resists are useful, for example, to form a patterning mask in the context of high-resolution patterning. Development can be accomplished using a halide-containing chemistry such as a hydrogen halide. A metal-containing resist film may be deposited on a semiconductor substrate using a dry or wet deposition technique. The resist film may be an EUV-sensitive organo-metal oxide or organo-metal-containing thin film resist. After exposure, the photopatterned metal-containing resist is developed using wet or dry development.
    Type: Application
    Filed: July 10, 2024
    Publication date: December 19, 2024
    Inventors: Samantha SiamHwa TAN, Jengyi YU, Da LI, Yiwen FAN, Yang PAN, Jeffrey MARKS, Richard A. GOTTSCHO, Daniel PETER, Timothy William WEIDMAN, Boris VOLOSSKIY, Wenbing YANG
  • Publication number: 20240395631
    Abstract: Some implementations described herein provide a method that includes forming a set of fins of a device, where the set of fins comprises an isolation fin disposed between a first fin and a second fin of the set of fins. The method also includes forming an isolation structure on at least one side of the isolation fin, with the isolation fin providing electrical isolation between the first fin and the second fin of the set of fins. Additionally, or alternatively, some implementations described herein provide a method that includes forming a funnel-shaped isolation structure between a first set of fins and a second set of fins. Additionally, or alternatively, some implementations described herein provide a method that includes forming, after forming a first gate structure and a second gate structure, an isolation structure between the first gate structure and the second gate structure.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 28, 2024
    Inventors: Yi Chen HO, Yu-Chuan CHEN, Chieh CHENG, Chi-Hsun LIN, Zheng-Yang PAN, Shahaji B. MORE
  • Publication number: 20240379450
    Abstract: In an embodiment, a device includes: an isolation region on a substrate; a first semiconductor fin protruding above the isolation region; a second semiconductor fin protruding above the isolation region; and a dielectric fin between the first semiconductor fin and the second semiconductor fin, the dielectric fin protruding above the isolation region, the dielectric fin including: a first layer including a first dielectric material having a first carbon concentration; and a second layer on the first layer, the second layer including a second dielectric material having a second carbon concentration, the second carbon concentration greater than the first carbon concentration.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Yi Chen Ho, Yiting Chang, Chi-Hsun Lin, Zheng-Yang Pan
  • Publication number: 20240371941
    Abstract: The present disclosure describes an exemplary fin structure formed on a substrate. The disclosed fin structure comprises an n-type doped region formed on a top portion of the substrate, a silicon epitaxial layer on the n-type doped region, and an epitaxial stack on the silicon epitaxial layer, wherein the epitaxial stack comprises a silicon-based seed layer in physical contact with the silicon epitaxial layer. The fin structure can further comprise a liner surrounding the n-type doped region, and a dielectric surrounding the liner.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shahaji B. MORE, Huai-Tei Yang, Zheng-Yang Pan, Shin-Cieh Chang, Chun-Chieh Wang, Cheng-Han Lee