Abstract: Disclosed herein is a method for monitoring the stability of process systems in semiconductor manufacturing using digital twins and neural networks. Digital twins of both individual and group process systems are created to identify sources of subsystem parameter changes over time and assess their precise impact on process performance. This method enhances operational efficiency, uniformity, and precision in complex semiconductor manufacturing processes.

Abstract: Disclosed herein is a method for matching process systems in semiconductor manufacturing by utilizing digital twins and neural networks. Digital twins of individual and group process systems are constructed, with the group digital twin guiding the matching of process systems within the group. Neural networks, trained on simulation and measured data, enhance computational efficiency, enabling precise matching and compatibility.

Abstract: A method for etching features in a stack below a patterned mask in an etch chamber is provided. The stack is cooled with a coolant with a coolant temperature below ?20° C. An etch gas is flowed into the etch chamber. A plasma is generated from the etch gas. Features are selectively etched into the stack with respect to the patterned mask.

Abstract: Disclosed herein are a system and method for real-time recipe generation in semiconductor manufacturing, utilizing digital twins, optimization techniques, and inverse neural networks. A search-and-match procedure uses metadata from simulated and real process cases to efficiently identify recipe and subsystem control parameters. When matches are unavailable, optimization algorithms or inverse neural networks refine these parameters. Applications include atomic layer etching (ALE) and other advanced manufacturing processes.

Abstract: A method for selectively etching silicon germanium with respect to silicon in a stack on a chuck in an etch chamber is provided. The chuck is maintained at a temperature below 15° C. The stack is exposed to an etch gas comprising a fluorine containing gas to selectively etch silicon germanium with respect to silicon.

Abstract: The present disclosure relates to an organosilica membrane with a porous intermediate layer and a method for preparing the same. The method includes: treating carbon nanotubes with an acid, washing, and drying to obtain carboxylated carbon nanotubes (COOH-CNTs); adding water to the COOH-CNTs and a SiO2—ZrO2 sol, and mixing uniformly to obtain a COOH-CNTs/SiO2—ZrO2 sol; coating the COOH-CNTs/SiO2—ZrO2 sol onto a tubular ceramic support, and calcining to obtain a ceramic support with a porous intermediate layer; and coating an organosilica sol onto the ceramic support with the porous intermediate layer, and performing a heat treatment to form a separation layer, thereby obtaining the organosilica membrane.

Abstract: Disclosed is a method and system for atomic layer etching (ALE) to enhance high aspect ratio (HAR) structure formation. The system includes a pressurized precursor buffer positioned proximate to a gas/precursor delivery unit. An in situ liner deposition step is interleaved at predetermined intervals within the ALE process cycles. A system controller monitors real-time precursor pressure within the buffer to determine and release a controlled volume of precursor into the chamber. This rapid in situ liner deposition, based on the precise volume of precursor introduced, facilitates enhanced profile control during HAR etching.

Abstract: Disclosed herein is a system and method for accelerated modulation of process chamber pressure, particularly advantageous in semiconductor manufacturing environments. The system utilizes a gas pressure control ring equipped with orifices and a series of responsive plungers. Plunger positions are adjusted through the application of alternating currents (AC) to coils, enabling rapid and precise pressure modulation within the chamber. The method further includes controlling coil currents and performing iterative adjustments to achieve a target pressure with high accuracy.

Abstract: The present disclosure provides a miniature electrostatic chuck (ESC) for die-to-wafer (D2W) bonding. The ESC can be manufactured using conventional semiconductor processes, incorporating through-silicon-via (TSV) and through-dielectric-via (TDV) structures. The ESC with different sizes can be attached to and detached from a multi-axis robotic arm, allowing optimized D2W bonding processes.

Abstract: A method for etching features in a stack below a patterned mask in an etch chamber is provided. The stack is cooled with a coolant with a coolant temperature below ?20° C. An etch gas is flowed into the etch chamber. A plasma is generated from the etch gas. Features are selectively etched into the stack with respect to the patterned mask.

Abstract: The present invention relates to a high-precision substrate alignment method and system for semiconductor bonding, utilizing advanced sensory systems, digital twin technology, and machine learning. Unique alignment marks, such as 2D barcodes and varied critical dimension (CD) grids, capture precise positional information of substrates in 3D space. This system optimizes movement trajectories for substrate bonding, significantly improving alignment accuracy and process efficiency.

Abstract: Disclosed herein is a semiconductor substrate bonder with a multi-zonal electrostatic chuck (ESC) that enables highly controllable pre-bonding from the substrate center progressively to the edge. Each ESC zone applies an independently controlled DC bias voltage for selective chucking and de-chucking, while pressurized gas or a retractable pin initiates center-based pre-bonding. This system is particularly suitable for hybrid bonding applications in semiconductor manufacturing.

Abstract: A method and system for atomic layer etching (ALE) are disclosed, utilizing a single gas or gas mixture without gas exchanges throughout the process. The plasma process chamber features an inductively coupled plasma (ICP) section for generating neutrals and a capacitively coupled plasma (CCP) section for ion-burst sputtering, separated by a grounded ion filter (GIF) that blocks ions while allowing neutrals and unreacted gases to pass. The system is optimized for forming high aspect ratio (HAR) structures.

Abstract: Disclosed is a method and system for atomic layer etching (ALE) that utilizes a single gas or mixed gases throughout the process without gas exchanges. The ALE process involves a continuous surface modification process, where the substrate surface undergoes chemical alteration, followed by intermittent ion-burst sputtering steps to remove the modified surface. The process eliminates undesired reactive ion etching (RIE), achieving an ideal ALE process through the use of a novel bias unit design. The disclosed method and system are particularly suitable for forming high aspect ratio (HAR) structures.

Abstract: This invention provides a method for improving the fabrication of 3D NAND devices by replacing the conventional oxide-nitride-oxide-nitride (ONON) stack with a silicon (Si) and silicon-germanium (SiGe) stack. This approach simplifies and accelerates the etching process by leveraging the lower bond strength and higher reactivity of Si and SiGe, while enabling effective layer replacement for electrical isolation and gate formation. The method enhances manufacturability and scalability of high-density 3D NAND devices.

Abstract: The present disclosure relates to a system and method for semiconductor manufacturing that utilizes a chamber pressure control ring equipped with integrated micro shutters. The system, managed by a proportional-integral-derivative (PID) control, enables rapid and precise modulation of chamber pressure, significantly outperforming conventional vacuum valve-based methods. This innovation improves process efficiency and reduces cycle times, particularly in advanced semiconductor processes such as atomic layer etching (ALE) and atomic layer deposition (ALD).

Abstract: The present disclosure relates to a system for semiconductor manufacturing, designed for rapid chamber pressure modulation through an array of small valves and pumps. The system incorporates micro shutters to achieve precise and rapid gas flow regulation. A system controller adjusts motor currents to compensate for nonuniformities resulting from incoming substrates and design constraints within the process system, thereby ensuring improved substrate uniformity during semiconductor manufacturing processes.

Abstract: Disclosed herein is a cost-effective atomic layer etching (ALE) system and method, featuring a simplified and rapid gas delivery system. The system reduces overall costs by eliminating the need for a gasbox and a manometer. Preset mass flow controllers (MFCs) and three-way valves precisely manage gas flow during both the surface modification and sputtering steps of the ALE process. By leveraging the self-limiting nature of ALE, the system enhances efficiency by controlling only the volume of delivered gases, without requiring steady-state chamber pressures.

Abstract: Disclosed herein is an AI-based system and method for optimizing lot dispatching in a semiconductor Fab using reinforcement learning (RL) and a Fab-wide digital twin. The system leverages a policy neural network and Monte Carlo Tree Search (MCTS) to enhance cycle time, output, and on-time delivery. The RL agent continuously trains in the background, adapting to changes in Fab operations, ensuring optimized real-time decision-making.