Abstract: A display device and a method of driving the same are provided. The display device according to an embodiment of the disclosure includes: a display panel including a plurality of pixel lines in an area A, an area B, and an area C; a panel driver configured to: supply input image data to pixel lines in the area A during a first period; supply black image data to pixel lines in the area B during a second period following the first period; and supply input image data to pixel lines in the area C during a third period following the second period; and a timing controller configured to adjust a first input image data to be supplied to a last pixel line in the area A to a first adjusted data based on a first compensation table.

Abstract: A display device and a method of driving the same are provided. The display device according to an embodiment of the disclosure includes: a display panel including a plurality of pixel lines in an area A, an area B, and an area C; a panel driver configured to: supply input image data to pixel lines in the area A during a first period; supply black image data to pixel lines in the area B during a second period following the first period; and supply input image data to pixel lines in the area C during a third period following the second period; and a timing controller configured to adjust a first input image data to be supplied to a last pixel line in the area A to a first adjusted data based on a first compensation table.

Abstract: A method of detecting a data bit depth and an interface device for a display device using the same are disclosed. The method includes confirming a physical connection between a transmitting terminal and a receiving terminal and then transmitting a clock data recovery (CDR) training pattern signal from the transmitting terminal to the receiving terminal, outputting clocks from a CDR circuit of the receiving terminal using the CDR training pattern signal, receiving an alignment training pattern signal subsequent to the CDR training pattern signal from the transmitting terminal to the receiving terminal, and counting bits of pixel data included in the alignment training pattern signal or the clocks and determining a data bit depth of input data based on a count result, in the interface receiving terminal.

Abstract: Disclosed is an apparatus and a method for controlling data interface. The apparatus for controlling data interface comprises: a transmitting terminal outputting signal including a CDR (Clock Data Recovery) training signal, an align training signal and display data sequentially; a receiving terminal inputting the signals from the transmitting terminal; and a Rx monitoring device detecting an abnormal status of the receiving terminal by monitoring an input timing signal and an operating status of the receiving terminal, and resetting the receiving terminal when the receiving terminal operates abnormally.

Abstract: Disclosed is an apparatus and a method for controlling data interface. The apparatus for controlling data interface comprises: a transmitting terminal outputting signal including a CDR (Clock Data Recovery) training signal, an align training signal and display data sequentially; a receiving terminal inputting the signals from the transmitting terminal; and a Rx monitoring device detecting an abnormal status of the receiving terminal by monitoring an input timing signal and an operating status of the receiving terminal, and resetting the receiving terminal when the receiving terminal operates abnormally.

Abstract: A method of detecting a data bit depth and an interface device for a display device using the same are disclosed. The method includes confirming a physical connection between a transmitting terminal and a receiving terminal and then transmitting a clock data recovery (CDR) training pattern signal from the transmitting terminal to the receiving terminal, outputting clocks from a CDR circuit of the receiving terminal using the CDR training pattern signal, receiving an alignment training pattern signal subsequent to the CDR training pattern signal from the transmitting terminal to the receiving terminal, and counting bits of pixel data included in the alignment training pattern signal or the clocks and determining a data bit depth of input data based on a count result, in the interface receiving terminal.

Abstract: A liquid crystal display and a driving method thereof are provided. The liquid crystal display includes: a liquid crystal display panel including a plurality of data lines, a plurality of gate lines crossing the data lines, and pixels arranged in m×n matrix; a register for defining polarity pattern information, frame rotation information, and line rotation information to determine a polarity of a data voltage charged in N lines, wherein N is a positive integer less than n; a timing controller for generating a polarity control signal to control polarities of data voltages charged in n lines of the liquid crystal display panel based on the information read from the register; and source drive ICs for converting the polarities of the data voltages supplied to the data lines in response to the polarity control signal.

Abstract: A liquid crystal display and a method of driving the same are disclosed. The liquid crystal display includes a timing controller, N source drive integrated circuits (ICs), where N is an integer equal to or greater than 2, N pairs of data bus lines, each of which connects the timing controller to each of the N source drive ICs in a point-to-point manner, a lock check line that connects a first source drive IC of the N source drive ICs to the timing controller and cascade-connects the N source drive ICs to one another, a feedback check line that connects a last source drive IC of the N source drive ICs to the timing controller.

Abstract: A liquid crystal display and a method of driving the same are disclosed. The liquid crystal display includes a timing controller, N source drive integrated circuits (ICs), where N is an integer equal to or greater than 2, N pairs of data bus lines, each of which connects the timing controller to each of the N source drive ICs in a point-to-point manner, a lock check line that connects a first source drive IC of the N source drive ICs to the timing controller and cascade-connects the N source drive ICs to one another, and a feedback lock check line connecting a last source drive IC of the N source drive ICs to the timing controller. A swing width of an output voltage of the timing controller increases in proportion to a distance between the timing controller and the N source drive ICs.

Abstract: A liquid crystal display and a method of driving the same are provided. The liquid crystal display includes a timing controller, N source drive integrated circuits (ICs), where N is an integer equal to or greater than 2, N pairs of data bus lines, each of which connects the timing controller to each of the N source drive ICs in a point-to-point manner, a lock check line that connects a first source drive IC of the N source drive ICs to the timing controller and cascade-connects the N source drive ICs to one another, and a feedback lock check line that connects a last source drive IC of the N source drive ICs to the timing controller.

Abstract: A liquid crystal display and a driving method thereof are provided. The liquid crystal display includes: a liquid crystal display panel including a plurality of data lines, a plurality of gate lines crossing the data lines, and pixels arranged in m×n matrix; a register for defining polarity pattern information, frame rotation information, and line rotation information to determine a polarity of a data voltage charged in N lines, wherein N is a positive integer less than n; a timing controller for generating a polarity control signal to control polarities of data voltages charged in n lines of the liquid crystal display panel based on the information read from the register; and source drive ICs for converting the polarities of the data voltages supplied to the data lines in response to the polarity control signal.

Abstract: A liquid crystal display and a method of driving the same are disclosed. The liquid crystal display includes a timing controller, N source drive integrated circuits (ICs), where N is an integer equal to or greater than 2, N pairs of data bus lines, each of which connects the timing controller to each of the N source drive ICs in a point-to-point manner, a lock check line that connects a first source drive IC of the N source drive ICs to the timing controller and cascade-connects the N source drive ICs to one another, and a feedback lock check line connecting a last source drive IC of the N source drive ICs to the timing controller. A swing width of an output voltage of the timing controller increases in proportion to a distance between the timing controller and the N source drive ICs.

Abstract: A liquid crystal display and a method of driving the same are provided. The liquid crystal display includes a timing controller, N source drive integrated circuits (ICs), where N is an integer equal to or greater than 2, N pairs of data bus lines, each of which connects the timing controller to each of the N source drive ICs in a point-to-point manner, a lock check line that connects a first source drive IC of the N source drive ICs to the timing controller and cascade-connects the N source drive ICs to one another, and a feedback lock check line that connects a last source drive IC of the N source drive ICs to the timing controller.

Abstract: A liquid crystal display and a method of driving the same are disclosed. The liquid crystal display includes a timing controller, N source drive integrated circuits (ICs), where N is an integer equal to or greater than 2, N pairs of data bus lines, each of which connects the timing controller to each of the N source drive ICs in a point-to-point manner, a lock check line that connects a first source drive IC of the N source drive ICs to the timing controller and cascade-connects the N source drive ICs to one another, a feedback check line that connects a last source drive IC of the N source drive ICs to the timing controller.