Abstract: An optical device includes a light receiving element for detecting light reflected and transmitted from a subject; a voltage part for providing a first bias voltage or a second bias voltage to the light receiving element; and a controller for controlling the voltage part so that the second bias voltage provided from the voltage part is synchronized with a light output of a light emitting part to be provided to the light receiving element.

Abstract: A semiconductor memory apparatus having a multi-bank memory array and data input/output method are disclosed. A plurality of memory banks are row-accessed at one time and a plurality of write enable signals are outputted to enable a buffer unit in accordance with an all bank selection signal and externally applied data are written to the plurality of memory banks through the enabled buffer unit. Also, a plurality of write enable signals are outputted to enable a buffer unit in accordance with an all bank selection signal and respective data outputted from the memory banks are checked to determine whether corresponding locations in the memory banks have the same logic levels so as to implement a simultaneous access of the memory banks. The same data is simultaneously written on corresponding same locations in the memory banks, thereby significantly decreasing the time required for the test.

Abstract: An hysteresis input buffer includes a first CMOS inverter generating a node signal, a second CMOS inverter coupled to the first CMOS inverter, inverting the node signal from the first CMOS inverter, and producing an intermediate signal, and a hysteresis control circuit coupled to the second CMOS inverter, receiving the intermediate signal, and producing an output signal having a low level during a predetermined delay time and a high level after the predetermined delay time has elapsed.

Abstract: Device and method for varying a bit line precharge voltage in a semiconductor memory, in which the bit line precharge voltage is varied with a chip temperature for improving a refresh characteristic, reducing a power consumption, the device including a temperature detector for detecting a change of a chip temperature of the semiconductor memory, a bit line precharge voltage generator for varying and forwarding the bit line precharge voltage in response to a temperature detection signal provided from the precharge voltage generator, and a sensing unit for receiving the bit line precharge voltage provided from the precharge voltage generator and sensing a data from the memory cell, the method including the steps of detecting a change of a chip temperature of the semiconductor memory, and dropping the bit line precharge voltage before forwarding the bit line precharge voltage if the chip temperature of the semiconductor memory is higher than a preset temperature.

Abstract: Disclosed is an internal voltage generator for applying stable working voltage to an internal circuit. The internal voltage generator comprises: a reference voltage generator for generating a reference voltage; a comparator for comparing the reference voltage with an internal voltage input into the internal circuit; a first switching element controlled by an output voltage of the comparator and coupled between a supply voltage terminal and an internal voltage input terminal in the internal circuit; a second switching element arranged in parallel with the first switching element and coupled between the supply voltage terminal and the internal voltage input terminal in the internal circuit; and an internal voltage controller for controlling a level of the internal voltage input into the internal circuit by controlling ON/OFF state of the second switching element according to an active mode and a standby mode.

Abstract: Provided is a sensing amplifier driving/controlling circuit for supplying pull-up/down voltage to a sensing amplifier of a semiconductor memory device, including: a first switching device for connecting internal voltage to the first driving line which in turn applies high voltage to the sensing amplifier; a second switching device for connecting an external voltage to the first driving line which in turn applies high voltage to the sensing amplifier; a third switching device for connecting ground voltage to a second driving line which in turn applies ground voltage to the sensing amplifier; a comparator having an inverse input terminal which is connected to the first driving line and a non-inverse input terminal which receives a reference voltage and thus the comparator is enabled when receiving first and second control signals; an inverter for inverting the first control signal and applying the inverse signal to the control input terminal of the first switching device; and a NAND gate for receiving the outpu

Abstract: An improved semiconductor memory apparatus which is capable of an increased data transmission ratio. The apparatus includes a memory array for storing data, a plurality of input/output pads and a data bus connected between data input/output pads for inputting/outputting the data stored in an external element and the memory array data is transferred between the input/output pads and first and second buffers in a time interval manner over basis of width N and between the memory array and the first and second buffer over a bus of width 2N.

Abstract: A programming section of a semiconductor memory device includes an external power source detecting circuit adapted for detecting an initial power supply and for generating a power-up signal, a gate control section for receiving the power-up signal from the external power source detecting circuit and for generating a first signal and a second signal, a programmable ROM cell for receiving the first and second signals from the gate control section and for generating an output, and a latch section for latching the output of the programmable ROM cell.