Abstract: Tuning information associated with a storage device of a plurality of storage devices is received. One or more characteristics associated with the storage device are determined. The tuning information and the one or more characteristics are provided to the plurality of storage devices, wherein providing the tuning information causes a set of the plurality of storage devices to apply the tuning information based on the one or more characteristics.

Abstract: Tuning information associated with a storage device of a plurality of storage devices is received. One or more characteristics associated with the storage device are determined. The tuning information and the one or more characteristics are provided to the plurality of storage devices, wherein providing the tuning information causes a set of the plurality of storage devices to apply the tuning information based on the one or more characteristics.

Abstract: Tuning information associated with a storage device of a plurality of storage devices is received. One or more characteristics associated with the storage device are determined. The tuning information and the one or more characteristics are provided to the plurality of storage devices, wherein providing the tuning information causes a set of the plurality of storage devices to apply the tuning information based on the one or more characteristics.

Abstract: A data storage device includes a first controller; a scale-out storage device; and an interface connected between the first controller and the scale-out storage device, wherein the first controller is configured to transmit, to the scale-out storage device through the interface, a first command including a command type and command information having a parameter with respect to the command type, wherein the scale-out storage device is configured to perform an operation corresponding to the first command, and wherein the scale-out storage device includes, a scale-out controller connected to the interface, a volatile memory connected to the scale-out controller, and a non-volatile memory connected to the scale-out controller.

Abstract: Systems and methods for Ethernet forwarding based on inferring topology in a G.8032 ring via control frames, implemented in a network element, include monitoring received control frames; determining which line port on the network element in the G.8032 ring is active based on the received control frames such that the topology of the G.8032 ring is inferred based on the received control frames; and forwarding data frames on the determined line port. The systems and methods can further include, subsequent to a fault and associated G.8032 protection which modifies ring blocks in the G.8032 ring, determining a change in the topology based on the received control frames; and updating the forwarding of the data frames based on the change.

Abstract: A data storage device includes a first controller; a scale-out storage device; and an interface connected between the first controller and the scale-out storage device, wherein the first controller is configured to transmit, to the scale-out storage device through the interface, a first command including a command type and command information having a parameter with respect to the command type, wherein the scale-out storage device is configured to perform an operation corresponding to the first command, and wherein the scale-out storage device includes, a scale-out controller connected to the interface, a volatile memory connected to the scale-out controller, and a non-volatile memory connected to the scale-out controller.

Abstract: A data storage device includes a first controller; a scale-out storage device; and an interface connected between the first controller and the scale-out storage device, wherein the first controller is configured to transmit, to the scale-out storage device through the interface, a first command including a command type and command information having a parameter with respect to the command type, wherein the scale-out storage device is configured to perform an operation corresponding to the first command, and wherein the scale-out storage device includes, a scale-out controller connected to the interface, a volatile memory connected to the scale-out controller, and a non-volatile memory connected to the scale-out controller.

Abstract: A data storage device includes a first controller; a scale-out storage device; and an interface connected between the first controller and the scale-out storage device, wherein the first controller is configured to transmit, to the scale-out storage device through the interface, a first command including a command type and command information having a parameter with respect to the command type, wherein the scale-out storage device is configured to perform an operation corresponding to the first command, and wherein the scale-out storage device includes, a scale-out controller connected to the interface, a volatile memory connected to the scale-out controller, and a non-volatile memory connected to the scale-out controller.

Abstract: Memory blocks of a nonvolatile memory device are managed by identifying a full memory block, determining whether a block life of the full memory block exceeds a threshold value, and upon determining that the block life of the full memory block exceeds the threshold value, selecting the full memory block as a target block for garbage collection. The threshold of the block life is determined using an average write distance of logical pages programmed in the nonvolatile memory device.

Abstract: A method for controlling a nonvolatile memory device includes reading a sub stripe including a plurality of sub pages stored in a first region, writing data stored in valid sub pages of the sub stripe to a second region different from the first region, and generating parity data using the data written to the second region and constituting a new sub stripe.

Abstract: An operating method of a memory controller includes classifying a plurality of blocks in a memory cell array included in a flash memory into a first group and a second group according to the number of error bits in data programmed to each of the blocks, and creating a combinational block by combining a first block from the first group with a second block from the second group.

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Abstract: A redundant array of inexpensive or independent disks (RAID) memory system comprises a nonvolatile memory device and a memory controller. The nonvolatile memory comprises a stripe block. The memory controller determines a value based on at least one of a program/erase (P/E) cycle and a read error frequency of the stripe block and determines whether to change a size of the stripe block based on the determined value.

Abstract: A method for controlling a nonvolatile memory device includes reading a sub stripe including a plurality of sub pages stored in a first region, writing data stored in valid sub pages of the sub stripe to a second region different from the first region, and generating parity data using the data written to the second region and constituting a new sub stripe.

Abstract: A computing system includes a host, a data source device, and a controller. The controller is configured to respond to a random access command from the host by setting information in a register that selects what data is to be accessed in the data source device. The controller then successively accesses the data in the data source device using the information that was set in the register.