Abstract: The present invention teaches how greater solder ball height can be achieved without the need to sacrifice areal density. The mold in which the solder is formed, is created in two steps. In a first exposure, a negative photoresist (preferably DFR) is patterned to form a conventional cylindrical mold. However, exposure and development time are adjusted in such a way that a layer of unexposed and undeveloped resist of reduced thickness remains covering the floor of the mold. This residual resist layer is given a second exposure and, after development, forms an annular insert in the bottom of the first mold. After the mold has been filled with solder (either through electroplating or by using solder paste) it is removed, the result being a solder bump made up of two contiguous coaxial cylinders the upper one having the larger diameter. After remelt, bumps having this shape form oblate spheroids rather than spheres.

Abstract: Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon.

Abstract: A new method and processing sequence is provided for the creation of interconnect bumps. A layer of passivation is deposited over a contact pad and patterned, creating an opening in the layer of passivation that aligns with the contact pad. A layer of UBM metal is deposited over the layer of passivation, the layer of UBM is overlying the contact pad and limited to the immediate surroundings of the contact pad. The central surface of the layer of UBM is selectively electroplated after which a layer of solder or solder alloy is solder printed over the electroplated surface of the layer of UBM. A solder flux or paste is applied over the surface of the solder printed solder compound or solder alloy. Flowing of the solder or solder alloy creates the solder bump of the invention.

Abstract: A new method and processing sequence is provided for the creation of interconnect bumps. A layer of passivation is deposited over a contact pad and patterned, creating an opening in the layer of passivation that aligns with the contact pad. A layer of UBM metal is deposited over the layer of passivation, the layer of UBM is overlying the contact pad and limited to the immediate surroundings of the contact pad. The central surface of the layer of UBM is selectively electroplated after which a layer of solder or solder alloy is solder printed over the electroplated surface of the layer of UBM. A solder flux or paste is applied over the surface of the solder printed solder compound or solder alloy. Flowing of the solder or solder alloy creates the solder bump of the invention.

Abstract: A method for bumping and backlapping a semiconductor wafer that has a multiplicity of solder bumps formed on an active surface of the wafer is disclosed. In the method, a preprocessed wafer that has a multiplicity of bond pads formed on a top surface is first provided, a under-bump-metallurgy (UBM) layer is then sputter deposited on top of the wafer surface, followed by the lamination of a dry film resist layer on top of the UBM layer. The dry film resist layer is then patterned with a multiplicity of openings exposing the multiplicity of bond pads, followed by the deposition of a solder material into the multiplicity of openings to form the solder bump's. A protective tape is then adhesively bonded to the top of the dry film resist layer before the wafer is positioned into a backlapping apparatus for removing of a preselected thickness from the backside of the wafer.

Abstract: A method for bumping and backlapping a semiconductor wafer that has a multiplicity of solder bumps formed on an active surface of the wafer is disclosed. In the method, a preprocessed wafer that has a multiplicity of bond pads formed on a top surface is first provided, a under-bump-metallurgy (UBM) layer is then sputter deposited on top of the wafer surface, followed by the lamination of a dry film resist layer on top of the UBM layer. The dry film resist layer is then patterned with a multiplicity of openings exposing the multiplicity of bond pads, followed by the deposition of a solder material into the multiplicity of openings to form the solder bumps. A protective tape is then adhesively bonded to the top of the dry film resist layer before the wafer is positioned into a backlapping apparatus for removing of a preselected thickness from the backside of the wafer.

Abstract: A method for forming an under bump metal, comprising the following steps. A semiconductor structure is provided having an exposed I/O pad. A patterned passivation layer is formed over the semiconductor structure, the patterned passivation layer having an opening exposing a first portion of the I/O pad. A dry film resistor (DFR) layer is laminated, exposed and developed to form a patterned dry film resistor (DFR) layer over the patterned passivation layer. The patterned dry film resistor (DFR) layer having an opening exposing a second portion of the I/O pad. The patterned dry film resistor (DFR) layer opening having opposing side walls with a predetermined profile with an undercut. A metal layer is formed over the patterned dry film resistor (DFR) layer, the exposed third portion of the I/O pad, and over at least a portion of the opposing side walls of the patterned dry film resistor (DFR) layer opening.

Abstract: A microelectronic method is described for optimizing the fabrication of optical and semiconductor array structures for high efficiency color image formation in solid-state cameras. Disclosed is an ordered fabrication sequence in which microlens formation precedes color filter layer formation to enable increased image light collection efficiency, to encapsulate and protect the microlens elements from chemical and thermal processing damage, to minimize topographical underlayer variations which would axially misalign or otherwise aberrate microlens elements formed on non-planar surfaces, and, to complete the most difficult steps early in the process to minimize rework and scrap. A CMOS, CID, or CCD optoelectronic configuration is formed by photolithographically patterning a planar-array of photodiodes on a Silicon or other III-V, II-VI, or compound semiconductor substrate.

Abstract: A method is disclosed for improving the bonding strength of wire bonds on semiconductor chips. Aluminum-silicon-copper is employed as the metal for wire bonding-pads. Openings are formed in the passivation layer over the bonding-pads. The exposed metal in the openings is treated with a fluorine containing F-plasma. A thin passivation film, with C, F, and O content is formed over the metal bonding pads. This protective film prevents the formation of pitting and staining of the bonding-pads when the wafer is subjected to repeated developing solutions during the color filter process performed for the CMOS image sensors, for example. Consequently, the wire bonds formed during the packaging of the chips are stronger and more reliable.

Abstract: A method for forming an optoelectronic microelectronic fabrication and an optoelectronic microelectronic fabrication fabricated in accord with the method. There is first provided a substrate having at minimum a first photoactive region and a second photoactive region formed therein. There is then formed over the substrate a patterned first color filter layer registered with the first photoactive region. There is then formed upon the patterned first color filter layer a first optically transparent planarizing encapsulant layer. There is then formed upon the first optically transparent planarizing encapsulant layer a patterned second color filter layer registered with the second photoactive region. Finally, there is then formed upon the patterned second color filter layer a second optically transparent planarizing encapsulant layer. The method contemplates an optoelectronic microelectronic fabrication fabricated in accord with the method.

Abstract: A microelectronic method is described for optimizing the fabrication of optical and semiconductor array structures for high efficiency color image formation in solid-state cameras. Disclosed is an ordered fabrication sequence in which microlens formation precedes color filter layer formation to enable increased image light collection efficiency, to encapsulate and protect the microlens elements from chemical and thermal processing damage, to minimize topographical underlayer variations which would axially misalign or otherwise aberrate microlens elements formed on non-planar surfaces, and, to complete the most difficult steps early in the process to minimize rework and scrap. A CMOS, CID, or CCD optoelectronic configuration is formed by photolithographically patterning a planar-array of photodiodes on a Silicon or other III-V, II-VI, or compound semiconductor substrate.

Abstract: A method for forming an image array optoelectronic microelectronic fabrication, and the image array optoelectronic microelectronic fabrication formed employing the method. There is first provided a substrate having a photoactive region formed therein. There is then formed over the substrate a patterned microlens layer which functions to focus electromagnetic radiation with respect to the photoactive region of the substrate. The patterned microlens layer is formed of a first material having a first index of refraction. Finally, there is then formed conformally upon the patterned microlens layer an encapsulant layer, where the encapsulant layer is formed of a second material having a second index of refraction no greater than, and preferably less than, the first index of refraction of the first material. The method of the present invention contemplates an image array optoelectronic microelectronic fabrication formed employing the method of the present invention.

Abstract: A method for forming an image array optoelectronic microelectronic fabrication. There is first provided a substrate. There is then formed at least in part over the substrate in a plane parallel to the substrate a bidirectional array of active image array optoelectronic microelectronic pixel elements. There is also formed over the substrate in the plane parallel to the substrate and contiguously extending from the bidirectional array of active image array optoelectronic microelectronic pixel elements an annular array of buffer image array optoelectronic microelectronic pixel elements. The annular array of buffer image array optoelectronic microelectronic pixel elements provides for uniform areal sensitivity of the bidirectional array of active image array optoelectronic microelectronic pixel elements.