Abstract: A semiconductor device includes a delay circuit and a column signal generation circuit. The delay circuit delays a write signal by a sum of a write latency time and a burst operation time to generate a write pulse, delays a read signal to generate a read pulse, and generates a pre-charge signal which is enabled after a predetermined period elapses from a time when the write signal is generated. The column signal generation circuit generates a column signal from a chip selection signal and a command/address signal when the write pulse or the read pulse is inputted to the column signal generation circuit. The column signal is a signal for selecting at least one memory cell included in one of a plurality of banks.

Abstract: A semiconductor device includes a delay circuit and a column signal generation circuit. The delay circuit delays a write signal by a sum of a write latency time and a burst operation time to generate a write pulse, delays a read signal to generate a read pulse, and generates a pre-charge signal which is enabled after a predetermined period elapses from a time when the write signal is generated. The column signal generation circuit generates a column signal from a chip selection signal and a command/address signal when the write pulse or the read pulse is inputted to the column signal generation circuit. The column signal is a signal for selecting at least one memory cell included in one of a plurality of banks.