Patents by Inventor Yang Weng
Yang Weng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11957064Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.Type: GrantFiled: October 18, 2022Date of Patent: April 9, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
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Publication number: 20240113032Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.Type: ApplicationFiled: April 25, 2023Publication date: April 4, 2024Inventors: Kai-Fung CHANG, Chin-Wei LIANG, Sheng-Feng WENG, Ming-Yu YEN, Cheyu LIU, Hung-Chih CHEN, Yi-Yang LEI, Ching-Hua HSIEH
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Patent number: 11928752Abstract: A processor device has a CPU cooperating with an input device and an output device, under control of stored instructions, and is arranged to receive service requests at the input device, assign service requests received in successive time periods to respective batches of requests; access stored service provider data to identify available service providers from among a pool of service providers; after completing the assignment of service requests to a batch, perform a matching process to endeavour to match each service request of the batch of requests to a service provider; and for each service provider to whom a match is made, output a notification of the respective potential match from the output device.Type: GrantFiled: September 21, 2022Date of Patent: March 12, 2024Assignee: GRABTAXI HOLDINGS PTE. LTD.Inventors: Kong-Wei Lye, Yang Cao, Swara Desai, Chen Liang, Xiaojia Mu, Yuliang Shen, Sien Y. Tan, Muchen Tang, Renrong Weng, Chang Zhao
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Publication number: 20240081157Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.Type: ApplicationFiled: November 6, 2023Publication date: March 7, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
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Publication number: 20240074328Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Applicant: United Microelectronics Corp.Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
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Patent number: 11911552Abstract: A combined bio-artificial liver support system, includes branch tubes that are connected in sequence: a blood input branch tube, an upstream tail end, a first plasma separation branch tube comprising at least a first plasma separator, a non-biological purification branch tube comprising at least a plasma perfusion device and a bilirubin adsorber, a biological purification branch tube comprising at least a hepatocyte culture cartridge assembly, and a plasma return branch tube, a downstream tail end of which is set as a blood output end.Type: GrantFiled: March 23, 2018Date of Patent: February 27, 2024Assignee: Southern Medical University Zhujiang HospitalInventors: Yi Gao, Mingxin Pan, Lei Feng, Yang Li, Lei Cai, Guolin He, Jun Weng, Qing Peng
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Publication number: 20240055385Abstract: A package structure and a method for fabricating the same are provided. The package structure includes a substrate, a semiconductor package and an adhesive body. The substrate has a first board surface and a second board surface. The semiconductor package has an upper surface and a lower surface, is disposed on the first board surface and electrically connected to the substrate through pins, and has a first vertical projection on the first board surface. An adhesive groove is disposed on the first board surface and is located in at least one portion of the first vertical projection and a periphery of the first vertical projection. The adhesive body is disposed in the adhesive groove, and protrudes to contact the lower surface, so as to fix the semiconductor package. The adhesive groove does not overlap with the pins, and the adhesive body does not contact the pins.Type: ApplicationFiled: May 11, 2023Publication date: February 15, 2024Inventors: KUO-HUA HSIEH, CHAO-CHIEH CHAN, MING-JHE WU, CHIH-YANG WENG
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Publication number: 20230307457Abstract: A semiconductor device having a standard cell comprises a first bottom transistor, a first top transistor, a second bottom transistor, a second top transistor, and a first bottom-transistor-level metal line. The first bottom transistor is in a first row. The first top transistor is disposed above the first bottom transistor in the first row. The first bottom transistor and the first top transistor share a first gate structure. The second bottom transistor is in a second row next to the first row. The second top transistor is disposed above the second bottom transistor in the second row. The second bottom transistor and the second top transistor share a second gate structure. The first bottom-transistor-level metal line extends laterally from a first source/drain region of the first bottom transistor to a source/drain region of the second bottom transistor.Type: ApplicationFiled: July 22, 2022Publication date: September 28, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Wei-Cheng KANG, Tzu-Hsuan CHANG, Wei-Yang WENG, Yu-Tzu CHENG, Huang-Chun HSU, Yu-Jung LIAO
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Patent number: 11656263Abstract: Effective feature set-based high impedance fault (HIF) detection is provided. Systems, methods and devices described herein present a systematic design of power feature extraction for HIF detection and classification. For example, power features associated with HIF events are extracted according to when a fault happens, how long it lasts, and the magnitude of the fault. Complementary power expert information is also integrated into feature pools. In another aspect, a ranking procedure is deployed in a feature pool for balancing information gain and complexity in order to avoid over-fitting of features. In aspects described herein, a logic-based HIF detector implements HIF feature extraction. To determine when an HIF occurs, the HIF detector calculates different quantities, such as active power and reactive power, based on a voltage and current time series, and uses the derivative of these quantities to tell when there is a potential change due to HIF.Type: GrantFiled: June 10, 2020Date of Patent: May 23, 2023Assignee: Arizona Board of Regents on behalf of Arizona State UniversityInventors: Qiushi Cui, Yang Weng, Khalil El-Arroudi, Syed Muhammad Yousaf Hashmy
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REINFORCEMENT LEARNING-BASED RECLOSER CONTROL FOR DISTRIBUTION CABLES WITH DEGRADED INSULATION LEVEL
Publication number: 20220129728Abstract: Reinforcement learning (RL)-based recloser control for distribution cables with degraded insulation level is provided. Utilities continuously observe cable failures on aged cables that have an unknown degraded basic insulation level (BIL). One of the root causes is the transient overvoltage (TOV) associated with circuit breaker reclosing. Since it is hard to model TOV due to its complexity, embodiments described herein provide a model-free stochastic control method for reclosers under the existence of uncertainty and noise. Concretely, to capture high-dimensional dynamics patterns, the recloser control problem is formulated herein by incorporating the temporal sequence reward mechanism into a deep Q-network (DQN). Meanwhile, physical understanding of the problem is embedded into the action probability allocation to develop an infeasible-action-space-elimination algorithm.Type: ApplicationFiled: October 26, 2021Publication date: April 28, 2022Applicant: Arizona Board of Regents on behalf of Arizona State UniversityInventors: Qiushi Cui, Yang Weng -
Publication number: 20210396799Abstract: High impedance fault (HIF) detection and location accuracy is provided. An HIF has random, irregular, and unsymmetrical characteristics, making such a fault difficult to detect in distribution grids via conventional relay measurements with relatively low resolution and accuracy. Embodiments disclosed herein provide a stochastic HIF monitoring and location scheme using high-resolution time-synchronized data in micro phasor measurement units (?-PMUs) for distribution network protection. In particular, a fault detection and location process is systematically designed based on feature selections, semi-supervised learning (SSL), and probabilistic learning.Type: ApplicationFiled: June 3, 2021Publication date: December 23, 2021Applicant: Arizona Board of Regents on behalf of Arizona State UniversityInventors: Qiushi Cui, Yang Weng
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Publication number: 20200393505Abstract: Effective feature set-based high impedance fault (HIF) detection is provided. Systems, methods and devices described herein present a systematic design of power feature extraction for HIF detection and classification. For example, power features associated with HIF events are extracted according to when a fault happens, how long it lasts, and the magnitude of the fault. Complementary power expert information is also integrated into feature pools. In another aspect, a ranking procedure is deployed in a feature pool for balancing information gain and complexity in order to avoid over-fitting of features. In aspects described herein, a logic-based HIF detector implements HIF feature extraction. To determine when an HIF occurs, the HIF detector calculates different quantities, such as active power and reactive power, based on a voltage and current time series, and uses the derivative of these quantities to tell when there is a potential change due to HIF.Type: ApplicationFiled: June 10, 2020Publication date: December 17, 2020Applicant: Arizona Board of Regents on behalf of Arizona State UniversityInventors: Qiushi Cui, Yang Weng, Khalil El-Arroudi, Syed Muhammad Yousaf Hashmy
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Patent number: 10813211Abstract: Traces on a PCB can be spaced closer together than in conventional layouts, which previously required the pair-to-pair spacing for the high-speed differential stripline signals to be at least 5H if the signals are originating from the same source and 7H when the signals on two pairs of transmission lines in the traces originate from different sources. Traces may be spaced closer together when, for example, a ratio of the core height to the prepreg height of the printed circuit board is approximately equal to one. Traces may be spaced closer together when, for example, a ratio of the trace spacing distance to the core height distance is less than approximately one.Type: GrantFiled: December 14, 2018Date of Patent: October 20, 2020Assignee: Dell Products L.P.Inventors: Pei-Yang Weng, Chun-Lin Liao, Bhyrav Murthy Mutnury
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Publication number: 20200196437Abstract: Traces on a PCB can be spaced closer together than in conventional layouts, which previously required the pair-to-pair spacing for the high-speed differential stripline signals to be at least 5H if the signals are originating from the same source and 7H when the signals on two pairs of transmission lines in the traces originate from different sources. Traces may be spaced closer together when, for example, a ratio of the core height to the prepreg height of the printed circuit board is approximately equal to one. Traces may be spaced closer together when, for example, a ratio of the trace spacing distance to the core height distance is less than approximately one.Type: ApplicationFiled: December 14, 2018Publication date: June 18, 2020Applicant: Dell Products L.P.Inventors: Pei-Yang Weng, Chun-Lin Liao, Bhyrav Murthy Mutnury
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Publication number: 20130269123Abstract: A process for dyeing ramie sliver, comprising: 1.) pretreatment: cooking the ramie sliver for 8-12 minutes in a cooking reagent in a bath ratio of 1:4-10, the cooking reagent is a 1-3 g/L aqueous solution of a penetrating agent; and 2.) dyeing: dyeing the cooked ramie sliver in an active dye in a bath ratio of 1:4-10. Also disclosed is a method for preparing ramie yarn. The ramie sliver dyed according to the present invention improves the properties of ramie fibers, such that the ramie fibers are less likely to break; and the ramie fibers are less likely to harden, avoiding poor drawing, needle breakage and missing stitches during carding and coalescing in post-procedures, thus achieving the purpose of smooth yarn spinning. Also disclosed is a method for preparing ramie colored-spun yarn.Type: ApplicationFiled: November 15, 2011Publication date: October 17, 2013Applicant: Hunan Huasheng Zhuzhou Cedar Co., Ltd.Inventors: Liming Liu, Zhi Ma, Yang Weng, Ying Kuang, Deming Chen, Ruizhi Zou
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Patent number: 8377902Abstract: The present invention relates to an RNAi compound and an expression plasmid for inhibiting expression of Thrombospondin-1, which comprises a target sequence selected from Thrombospondin-1 gene. The present invention also related to a pharmaceutical composition comprising the RNAi compound and applications thereof. The RNAi compound can reduce the expression of Thrombospondin-1 to activate immune responses. In addition, the present invention also disclosed that an RNAi compound targeted to Thrombospondin-1 gene can delay tumor progression.Type: GrantFiled: January 6, 2011Date of Patent: February 19, 2013Assignee: National Cheng Kung UniversityInventors: Ming-Derg Lai, Shih-Shien Huang, Meng-Chi Yen, Chi-Chen Lin, Tzu-Yang Weng
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Publication number: 20110166199Abstract: The present invention relates to an RNAi compound and an expression plasmid for inhibiting expression of Thrombospondin-1, which comprises a target sequence selected from Thrombospondin-1 gene. The present invention also related to a pharmaceutical composition comprising the RNAi compound and applications thereof. The RNAi compound can reduce the expression of Thrombospondin-1 to activate immune responses. In addition, the present invention also disclosed that an RNAi compound targeted to Thrombospondin-1 gene can delay tumor progression.Type: ApplicationFiled: January 6, 2011Publication date: July 7, 2011Applicant: National Cheng Kung UniversityInventors: Ming-Derg Lai, Shih-Shien Huang, Meng-Chi Yen, Chi-Chen Lin, Tzu-Yang Weng
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Publication number: 20100005730Abstract: A building energy storage and conversion apparatus includes at least a control unit, an electric power conversion unit, an energy conversion unit and a thermoelectric conversion unit to regulate energy sources of the electric power conversion unit. The energy conversion unit generates cold/heat energy which is stored through a heat storage equipment (for cold/heat energy). The cold/heat energy can be released when needed. When the cold/heat energy is in a surplus state, it can be converted to electric power through the thermoelectric conversion unit or stored in the form of electric power. Thus energy resources can be converted and utilized in an optimal fashion to achieve energy self-sufficiency of a building. Moreover, energy exchange with other buildings in the neighborhood can be done to balance demand and supply.Type: ApplicationFiled: July 11, 2008Publication date: January 14, 2010Inventors: Kuo Liang Weng, Ou Yang Weng, Ching Ying Tsai, Chien Lun Weng, Ling Hua Weng, Ching Ju Weng, Shih Wei Lin
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Publication number: 20070178920Abstract: A system capable of remotely controlling a multimedia device through the Internet includes a remote control device including a first network module electrically connected to the Internet, a local device including a second network module electrically connected to the Internet, a database for storing settings data of the local device, and a software installed in the remote control device including a transformation code for interpreting commands outputted from the first network module to the second network module into a plurality of command contents to update the database.Type: ApplicationFiled: April 17, 2006Publication date: August 2, 2007Inventors: Po-Chih Lin, Chia-Yang Weng