Abstract: A cell structure of a silicon carbide MOSFET device, comprising a first conductivity type drift region (3) located above a first conductivity type substrate (2). A main trench is provided in the surface of the first conductivity type drift region (3); a Schottky metal (4) is provided on the bottom and sidewalls of the main trench; a second conductivity type well region (7) is provided in the surface of the first conductivity type drift region (3) and around the main trench; a source region (8) is provided in the surface of the well region (7); a source metal (10) is provided above the source region (8); a gate insulating layer (6) and a gate (5) split into two parts are provided above the sides of the source region (8), the well region (7), and the first conductivity type drift region (3) close to the main trench.

Abstract: The disclosure discloses a composite fluorescent ceramic, a preparation method of the composite fluorescent ceramic and a light emitting device related to the technical field of optical components. The device includes a luminescent phase, a matrix phase and pores, the luminescent phase includes multiple luminescent crystal grains bonded together, the matrix phase includes multiple matrix crystal grains bonded together, the matrix phase and the luminescent phase are interspersed with each other and distributed in a composite fluorescent ceramic, at least part of pores are distributed in the luminescent phase, at least part of pores are distributed in the matrix phase, and at least part of pores are distributed between the luminescent phase and a Al2O3 matrix phase. The composite fluorescent ceramic may have high scattering performance.

Abstract: The disclosure relates to a method and a system for predicting the operation time of sparse matrix vector multiplication. The method comprises constructing a convolutional neural network comprising an input layer, a feature processing layer, a data splicing layer and an output layer for outputting prediction results. The method further comprises acquiring a plurality of groups of sparse matrices with known sparse matrix vector multiplication operation time as sample data, inputting the sample data into the convolutional neural network to train the convolutional neural network, and inputting the sparse matrix to be classified into the trained convolutional neural network to realize the prediction of the operation time of sparse matrix vector multiplication.

Abstract: A multiphase fluorescent ceramic and a preparation method therefor. Spinel is provided in a multiphase fluorescent ceramic including an alumina matrix and fluorescent particles, the spinel is distributed between alumina grain boundaries, and the exciting light irradiated into the multiphase fluorescent ceramic can be scattered, thereby facilitating further improvement in the luminous efficiency of the multiphase fluorescent ceramic.

Abstract: A light reflecting material, a reflecting layer and a preparation method therefor; the light reflecting material comprises glass powder particles (1), diffuse reflection particles, ultra-fine nano particles and an organic carrier; the particle size of the glass powder particles (1) is ?5 ?m, the particle size of the diffuse reflection particles is 0.1 ?m to 0.2 ?m, and the particle size of the ultra-fine nano particles is 0.01 ?m to 0.05 ?m. The glass powder particles (1), diffuse reflection particles and ultra-fine nano particles the particle sizes of which decrease progressively in sequence by one order of magnitude are used as the raw materials of the reflecting layer, without deceasing the adhesion between the reflecting layer and a substrate, the surface area within the reflecting layer that may cause reflection or refraction is increased to obtain better reflectivity.

Abstract: We herein describe a semiconductor device sub-assembly comprising at least two power semiconductor devices and a contact of a first type. A first power semiconductor device is located on a first side of the contact of a first type, and a second power semiconductor device is located on a second side of the contact of a first type, where the second side is opposite to the first side.

Abstract: A method and device for simulating microstructure evolution of a material based on solution in an exponential time-difference format. The method includes: establishing a reaction rate theory model for substance defects, wherein the model is expressed with equations that comprise linear terms having coefficients characterized with matrixes; and iteratively solving the equations by using an exponential time-difference format, wherein during the iterative solving, the linear terms with exponential powers of the matrixes as the coefficients are integrated. Since a rate theory is not limited by spatial-temporal scales, the advantages of the rate theory can be significantly reflected when the microstructure evolution is simulated under a high damage dose condition; and then, the equations are solved by using the exponential time-difference format, with a solved result better in accuracy and higher in precision.

Abstract: A semiconductor device comprising: a plurality of semiconductor chips; a first conductor and a second conductor arranged at opposite sides of the semiconductor chips, wherein the second conductor comprises a plurality of pillars, and wherein each of the semiconductor chips comprises: a first surface facing the first conductor; a first electrode arranged on the first surface and electrically coupled to the first conductor; a second surface opposite to the first surface; a second electrode arranged on the second surface and electrically coupled to a respective one of the pillars, and a control electrode arranged on the second surface and configured to switch a current flowing between the first electrode and the second electrode; a circuit board comprising openings penetrated by the plurality of pillars, wherein the circuit board further comprises an electrically insulating layer, a first conductive film and a second conductive film.

Abstract: There is provided a semiconductor device 1, comprising: a housing comprising a first housing electrode 5 and a second housing electrode 4 which are arranged at opposite sides of the housing, wherein the first housing electrode 5 comprises an electrode plate; and a plurality of semiconductor units 30 arranged within the housing between the first and second housing electrodes 4, 5 and coupled to at least one of the first and second housing electrodes by pressure; a thermal coupler 17 arranged within the housing between the plurality of semiconductor units 30 and the electrode plate of the first housing electrode 5; a first array of pillars 10 extending between the plurality of semiconductor units 30 and the thermal coupler 17, and electrically coupled to the plurality of semiconductor units 30, respectively; and a second array of pillars 18 extending between the thermal coupler 17 and the electrode plate of the first housing electrode 5, wherein the first array of pillars 10 are electrically coupled to the elec

Abstract: There is provided a semiconductor device 1 which comprises: a housing comprising a first housing electrode 5 and a second housing electrode 4 which are arranged at opposite sides of the housing; a plurality of semiconductor units 30 arranged within the housing between the first and second housing electrodes 4, 5; a plurality of pressure means 40 for applying pressure to the plurality of semiconductor units 30, respectively, wherein the plurality of pressure means 40 are arranged between the plurality of semiconductor units 30 and the first housing electrode 5; a first conductive structure 14 arranged between the plurality of pressure means 40 and the plurality of semiconductor units 30, wherein the plurality of semiconductor units 30 are electrically connected in parallel between the second housing electrode 4 and the first conductive structure 14; and a second conductive structure 18 configured to provide a current flow path from the first conductive structure 14 to the first housing electrode 5, the second

Abstract: A wavelength conversion device and a light source system, including: a substrate; a first light-emitting portion disposed on the substrate, wherein the first light-emitting portion includes a first light guide area and a counterweight area provided on the same layer as the first light guide area, the first light guide area being used for guiding first light, and the counterweight area being used for making the weight distribution of the wavelength conversion device substantially uniform; and a second light-emitting portion provided on the substrate on the same side as the first light-emitting portion, the second light-emitting portion including a conversion area, and the conversion area being used to convert at least a part of excitation light into excited light for emission when the excitation light is received.

Abstract: There is provided a semiconductor device 1, comprising: a housing comprising: a first housing electrode 4 and a second housing electrode 5 arranged at opposite sides of the housing, and a tubular housing element 8 arranged between the first and second housing electrodes 4, 5 and configured to electrically isolate the first and second housing electrodes 4, 5 from one another; at least one semiconductor chip 20 arranged within the housing between the first and second housing electrodes 4, 5; and a metal explosion shield 12 arranged within the housing, wherein the metal explosion shield 12 is configured to extend into a space formed between the at least one semiconductor chip 20 and the tubular housing element 8 such that the metal explosion shield surrounds the at least one semiconductor chip 20.

Abstract: The present disclosure provides a semiconductor device 1, comprising: a housing comprising an internal space; at least one semiconductor chip 20 arranged inside the housing; and a separator 13 arranged inside the housing and configured to separate the internal space of the housing into a first chamber 11 and a second chamber 12, wherein the at least one semiconductor chip 20 is arranged within the first chamber 11; wherein the separator 13 comprises a deformable portion 15, and the deformable portion 15 is configured to deform when a pressure difference between the first and second chambers 11, 12 exceeds a threshold differential pressure or a temperature at the deformable portion 15 exceeds a threshold temperature, so as to transform the first chamber 11 from a hermetically sealed chamber to an open chamber in fluid communication with the second chamber 12.

Abstract: There is provided a semiconductor device 1, comprising: a housing comprising a housing electrode 4; and at least one semiconductor chip 20 arranged within the housing; wherein the housing electrode 4 comprises a deformable portion 15, and the deformable portion 15 is configured to deform when a pressure difference between an interior and an exterior of the housing exceeds a threshold differential pressure or a temperature at the deformable portion exceeds a threshold temperature, so as to transform the housing from a hermetically sealed housing to an open housing in fluid communication with the exterior.

Abstract: There is provided a semiconductor device 1, comprising: a housing comprising a first housing electrode 4 and a second housing electrode 5 arranged at opposite sides of the housing; and a plurality of semiconductor units 30 arranged within the housing between the first and second housing electrodes 4, 5 and coupled to at least one of the first and second housing electrodes 4, 5 by pressure, wherein the plurality of semiconductor units 30 comprise a first semiconductor unit 30-1 and a second semiconductor unit 30-2 neighbouring the first semiconductor unit 30-1; wherein the first and/or second housing electrode comprises a plurality of pillars 10, and the plurality of pillars comprise a first pillar 10-1 and a second pillar 10-2 electrically coupled to the first and second semiconductor units 30-1, 30-2, respectively, and wherein a surface 16 of the first housing electrode 4 comprises a groove 15, and a width W1 of the groove 15 is less than a spacing S2 between the first pillar 10-1 and the second pillar 10-2.

Abstract: There is provided a semiconductor device 100, comprising: at least one semiconductor chip 5, and a structure 2 thermally coupled to the at least one semiconductor chip 5, wherein the structure 2 comprises a surface located within an interior of the semiconductor device, and the surface comprises a groove 12; and a sensor 16 comprising an optical fibre 13 passing through the groove 12, wherein the sensor 16 is configured to sense a temperature of the at least one semiconductor chip 5.

Abstract: A cell structure of a silicon carbide MOSFET device, comprising a first conductivity type drift region (3) located above a first conductivity type substrate (2). A main trench is provided in the surface of the first conductivity type drift region (3); a Schottky metal (4) is provided on the bottom and sidewalls of the main trench; a second conductivity type well region (7) is provided in the surface of the first conductivity type drift region (3) and around the main trench; a source region (8) is provided in the surface of the well region (7); a source metal (10) is provided above the source region (8); a gate insulating layer (6) and a gate (5) split into two parts are provided above the sides of the source region (8), the well region (7), and the first conductivity type drift region (3) close to the main trench.

Abstract: We describe herein a high voltage semiconductor device comprising a power semiconductor device portion (100) and a temperature sensing device portion (185). The temperature sensing device portion comprises: an anode region (140), a cathode region (150), a body region (160) in which the anode region and the cathode region are formed. The temperature sensing device portion also comprises a semiconductor isolation region (165) in which the body region is formed, the semiconductor isolation region having an opposite conductivity type to the body region, the semiconductor isolation region being formed between the power semiconductor device portion and the temperature sensing device portion.

Abstract: We herein describe a semiconductor device sub-assembly comprising at least two power semiconductor devices and a contact of a first type. A first power semiconductor device is located on a first side of the contact of a first type, and a second power semiconductor device is located on a second side of the contact of a first type, where the second side is opposite to the first side.

Abstract: The disclosure relates to a method and a system for predicting the operation time of sparse matrix vector multiplication. The method comprises constructing a convolutional neural network comprising an input layer, a feature processing layer, a data splicing layer and an output layer for outputting prediction results. The method further comprises acquiring a plurality of groups of sparse matrices with known sparse matrix vector multiplication operation time as sample data, inputting the sample data into the convolutional neural network to train the convolutional neural network, and inputting the sparse matrix to be classified into the trained convolutional neural network to realize the prediction of the operation time of sparse matrix vector multiplication.